cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 314

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

13.0 AALx Interworking
13.2 AALx SEG Operation
13.2.1 AALx Network Centric Operation—(EXTERNAL_SCH = 0)
13-4
13.2 AALx SEG Operation
To support AALx operation, HPORT_ID and AALx_EN are added to the
segmentation VCC table entry as follows: AALx_EN is added to bit 21 of word 5
and HPORT_ID is added to word 5 (of a CBR mode connection) bits 26 through
30. HPORT_ID is only used in network centric scheduling (that is,
EXTERNAL_SCH = 0). (The PCI addresses for each AALx are stored in internal
memory as shown in
are maintained. An edge detection circuit increments each counter. The counter is
decremented after a read of the cell. A non 0 count indicates a cell is available for
transmit from the corresponding AALx. The counter size is programmable up to
16 cells via the AALx_CTRL(EGRESS_DEPTH) register.
a write occurs on a full condition, HSEGOVFLx output pulses to a logic high for
one clock period. The counter should prevent rollover or roll-under.
In this mode, the AALx traffic stream is scheduled using a CBR connection, with
bandwidth reserved in the schedule table. The Segmentation block, processing a
CBR connection from the Scheduler with AALx_EN set high, looks up the
HPORT_ID field to identify which HFIFOWRx counter check to determine if a
cell is available from that AALx. If it is, the PCI address for that AALx is looked
up from the corresponding internal memory address and the entire cell (52 bytes)
with modified ATM Header word is read across the PCI bus. This process is
similar to the virtual FIFO buffer scheduling mode as exists today. However, no
rate matching using the SCH_OPT bit is required, the CURR_PNTR field is a
Don’t Care, and the header is included in the cell read across the PCI bus, as
opposed to being read from the VCC table.
the following:
Six shadow FIFO buffer counters, corresponding to each HFIFOWRx input,
Each counter is reset by either SEG_RESET or a separate reset per port. When
To set up a connection for the AALx traffic stream in this mode, the user does
• Populates the schedule table with the connection’s VCC index.
• Sets the connection’s VCC table entries: AALx_EN = 1, HPORT_ID, and
• Writes the AALx’s FIFO buffer PCI address to internal memory.
• Writes the ATM header into VCC entry.
• To enable the AALx traffic stream to be transmitted, sets the connection’s
SCH_MODE = CBR.
VCC table RUN bit high.
Mindspeed Technologies
Table
4-6.)
ATM ServiceSAR Plus with xBR Traffic Management
™
28236-DSH-001-B
CN8236