cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 255

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 9-1. Memory Bank Size
28236-DSH-001-B
BANKSIZE
111
110
101
100
011
010
001
000
Bank Memory
Organization
512 K × 32
256 K × 32
128 K × 32
64 K × 32
32 K × 32
16 K × 32
2 M × 32
1 M × 32
9.2 Memory Bank Characteristics
The external memory is organized in one to four banks of up to 2 MB each. The
system can use any number of banks to fulfill the memory requirements; the only
stipulation is that the banks must be of the same size and organization. The local
processor and host processor select between the banks using the PBSEL[1:0]
inputs. PBSEL[1:0] is sourced by local processor Host processor sources PCI
Address Bits. BANKSIZE[2:0] (bits 23–21) in the CONFIG0 register denote the
size of the memory banks and allow the CN8236 to incorporate the various bank
sizes into contiguous memory.
control bits.
SRAM devices, and by_16 devices. Grounding the RAMMODE input selects the
by_4 or by_8 mode of operation, while pulling RAMMODE to a logic 1 selects
by_16 operation. When by_16 operation is selected, the MWE[3:0]* outputs
become byte enables for both reads and writes. When reading local memory,
entire 32-bit words are always read, regardless of memory type.
a typical 500-KB bank implementation using by_8 SRAM devices.
shows a typical bank using by_16 RAM. To connect different sized RAM banks,
simply use more or less address bits; all other control remains the same.
NOTE:
The memory controller is designed to work with standard by_8 devices, by_4
The number and type of SRAM chips used affect the address and data bus
capacitance and, therefore, the AC timing specifications and the required
SRAM speed. The use of by_4 devices causes more address bus loading
than the use of by_8 or by_16 devices. See
timing information.
Mindspeed Technologies
Size (Bytes)
Total Bank
512 K
256 K
128 K
64 K
8 M
4 M
2 M
1 M
Address Bits
PBSEL[1:0]
A[22:21]
A[21:20]
A[20:19]
A[19:18]
A[18:17]
A[17:16]
or PCI
Table 9-1
—
—
™
gives the coding of the BANKSIZE[2:0]
Future expansion
Two 1 M × 16, one 1 M × 32
Four 512 K × 8
Two 256 K × 16, Eight 256 K × 4
Four 128 K × 8
Two 64 K × 16, Eight 64 K × 4
Four 32 K × 8
Two 16 K × 16, Eight 16 K × 4
Chapter
Typical Implementation
9.2 Memory Bank Characteristics
9.0 Local Memory Interface
16.0, for detailed
Figure 9-2
Figure 9-3
shows
9-3