cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 386

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

16.0 Electrical and Mechanical Specifications
16.1 Timing
Table 16-7. CN8236 Memory Interface Timing
16-10
Symbol
NOTE(S):
(1)
(2)
(3)
(4)
5. SYSCLK shown for reference only.
t
t
t
t
t
t
dodmoe
moedoe
t
t
mweov
t
mweov
t
mcsov
t
mcsov
t
mweh
mwrh
moeh
t
t
t
mwel
t
moel
t
mwrl
t
t
t
dod
t
aov
doe
t
aov
dov
dis
dh
wc
See
T = t
Insert 1 clock cycle for 2-cycle memory (1 wait state).
See
rc
w
Figure 16-7
Figure 16-8
s
for single cycle memory (no wait states), T = 2t
READ Cycle Time
LADDR[18:0] Output Valid
MCS[3:0]* Output Valid
MWE* Byte Enables Output Valid
(RAMMODE = 1)
MOE* Low
MOE* High
LDATA Output Disable
LDATA Input Setup
LDATA Input Hold
LDATA Driven by SAR
LDATA Disable to MOE* Low
MOE* High to LDATA Driven
WRITE Cycle Time
MWR*, MWE[3:0]* Width
LADDR[18:0] Output Valid
MCS[3:0]* Output Valid
MWE* Byte Enables Output Valid
(RAMMODE = 1)
LDATA Output Valid
MWE[3:0]* Low
MWE[3:0]* High
MWR[3:0]* Low
MWR[3:0]* High
for waveforms.
for waveforms.
(1)
(1)
Parameter
(4)
( 4)
(4)
(4)
(2)
(1)
(2)
(1)
( 4)
(1)
(1)
(1)
(4)
(2, 4)
(1)
(4)
(1)
(1)
Mindspeed Technologies
(1)
(1)
Memory Write Timing
Memory Read Timing
4 banks of by_8
T/2 – 2
T/2 – 2
T/2-2
s
Min
—
—
—
12
—
—
for 2-cycle memory, (1 wait state).
T
1
1
1
5
0
0
6
T
1
1
1
1
SRAM
Max
—
10
10
10
17
10
—
—
—
—
—
—
—
10
10
10
10
16
16
7
1
1
ATM ServiceSAR Plus with xBR Traffic Management
T/2 – 2
2 banks of by_8
Min
—
—
—
11
—
—
—
—
T
1
1
1
5
0
0
7
T
1
1
1
1
™
SRAM
Max
—
16
—
—
—
—
—
—
—
10
16
16
8
8
8
8
6
8
8
8
1
1
T/2 – 2
1 bank of by_8
Min
—
—
—
11
—
—
—
—
T
1
1
1
5
0
0
8
T
1
1
1
1
SRAM
28236-DSH-001-B
Max
—
15
—
—
—
—
—
—
—
10
16
16
7
7
7
7
6
7
7
7
1
1
CN8236
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns