cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 308

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 ATM UTOPIA Interface
12.8 Loopback Mode
Figure 12-8. Source Loopback Mode Diagram
12-18
SYSCLK
12.8 Loopback Mode
The physical interface can be internally looped by setting the FR_LOOP bit in the
CONFIG0 register to a logic high. This mode uses the internal system clock for
operation; therefore, a framer clock is not needed during loopback operation.
and control signals so the path from the segmentation coprocessor to the
reassembly coprocessor can be tested. The internal connections of the PHY
device interface signals are connected, as
side is put into the UTOPIA Mode and the receive side is put into the Reverse
UTOPIA Mode.
RxClav are three-stated, so there are no output conflicts with other devices
connected to these signals.
NOTE:
Transmit
When the FR_SRC_LOOP signal equals 1, the interface loops back the data
In this mode, the outputs of the chip, TxData, TxPar, TxSOC, TxEN*, and
UTOPIA
Reverse
UTOPIA
Receive
Side in
Side In
Mode
Mode
A reset of the reassembly coprocessor is required after the changing of the
FR_LOOP bit, because this changes the source of the clock to the physical
interface circuitry. To accomplish this reset, assert RSM_CTRL0
(RSM_RESET).
Mindspeed Technologies
RXADDR[4:0]
TXADDR[4:0]
RXD[15:0]
TXD[15:0]
RXCLAV
TXCLAV
RXSOC
TXSOC
RXPAR
TXPAR
RXEN*
TXEN*
ATM ServiceSAR Plus with xBR Traffic Management
™
Figure 12-8
illustrates. The transmit
28236-DSH-001-B
CN8236
8236_077