cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 131

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
5.4.4 Linked Data Buffers
Figure 5-14. Data Buffer Structures
28236-DSH-001-B
NOTE(S):
No user fields in buffers - payload data only.
Buffer Descriptors
(Host Memory)
NEXT_PTR
BUFF_PTR
NEXT_PTR
BUFF_PTR
BUFF_PTR
NULL
After the free buffer queue has returned pointers to a buffer descriptor and a cell
buffer, the reassembly coprocessor writes payload data to the buffer.
buffers do not contain any control information. A pointer in a separate buffer
descriptor structure links the buffers.
descriptor, which has a pointer (BUFF_PTR) pointing to a buffer. The use of this
buffer locating mechanism offers a layer of indirection in buffer assignment that
maximizes system architecture flexibility.
the buffer descriptor, which is written by the reassembly coprocessor when the
current buffer is completed. The host writes the second word of the buffer
descriptor to point to the next associated data buffer. The link pointer of the last
buffer descriptor in a chain is written to NULL.
VCC table entry for that channel is a logic low.
NOTE:
The linked cell buffers contain the payload portions of the ATM cells. The
Thus, the pointer in the free buffer queue (BD_PNTR) points to a buffer
Figure 5-14
The data buffers are linked by a pointer (NEXT_PNTR) in the first word of
The link pointer (NEXT_PNTR) is not written if the LNK_EN bit in the RSM
Only the data buffers are affected by big/little endian processing. The
buffer control structures (that is, the buffer descriptors, free buffer queue
base table, and free buffer queues) are the same in both big and little
endian modes.
Mindspeed Technologies
illustrates this structure.
™
(Host Memory)
Buffers
5.0 Reassembly Coprocessor
5.4 Buffer Management
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