cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 276

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

10.0 Local Processor Interface
10.6 Standalone Operation
10.6.1 Microprocessor Interface for Multiple Physical Devices
Figure 10-11. SAR/Peak 8 Control Connections
10-18
NOTE(S):
(1)
CN8236 (SAR) outputs 5 bits, CN8228 (Peak8) only uses 4 bits.
(HAD[10:3])PADDR[7:0]
CN8236 (SAR)
PADDR[12:8]
PDATA[7:0]
Multi-phy or extended addressing for a PHY is provided through a PHY page
mechanism. This allows address bits to be appended to PHY control access
without increasing the size of the PHY memory map as seen by the PCI. The
PHY BANK field in the CONFIG1 control register provides up to 5 bits of page
addressing for a total of 14 bits of PHY addressing. The contents of PHY BANK
are placed on LADDR[13:9] during PHYCS1 or PHYCS2 accesses.
illustrates control connections between the SAR and a PHY device.
PWAIT*
PWNR
PRST*
PINT*
PCLK
PCS*
PAS*
Mindspeed Technologies
Pullup
ATM ServiceSAR Plus with xBR Traffic Management
Pullup
ADDR[12:8]
ADDR[7:0]
DATA[7:0]
CS*
AS*
WNR
MCLK
INT*
SYNCMODE
RESET*
™
CN8228 (PEAK8)
(1)
28236-DSH-001-B
Figure 10-11
CN8236
8236_114