cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 128

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

5.0 Reassembly Coprocessor
5.4 Buffer Management
5.4.1 Host vs. Local Reassembly
5.4.2 Scatter Method
5-18
5.4 Buffer Management
Once CPCS-PDU processing has been implemented, the cell payloads are written
to data buffers. Each channel retrieves the location of its buffers from one of 32
free buffer queues. The reassembly coprocessor tracks the location of the buffers
from the VCC table entry for that channel.
NOTE:
Data buffers can reside in both host and SAR-shared memory. The majority of
user data traffic should be reassembled in host memory. SAR-shared memory
reassembly is intended for low bandwidth management and control functions,
such as OAM and signaling. This allows an optional local processor to off-load
these network management functions from the host, focusing host processing
power on the user application.
The CN8236 uses an intelligent scatter method to write cell payload data to host
memory. During reassembly to host memory, the reassembly coprocessor uses the
DMA coprocessor to control the scatter function. The reassembly coprocessor
controls the incoming DMA block during scatter DMA to host memory.
host memory, one in SAR-shared memory, and one in internal memory. The
linked cell buffers (HCELL_BUFF) and reassembly buffer descriptors reside in
host memory, and the free buffer queues (HFR_BUFF_QU) reside in SAR-shared
memory. The free buffer queues also have an associated free buffer queue base
table. This table is in internal memory. The CN8236 allows for up to 32
independent free buffer queues.
Data buffers are supplied according to the mechanisms detailed below.
Four data structures are maintained, as illustrated in
The process cycle time of a read transaction across the PCI bus is much
longer than a write transaction, due to the PCI bus being held in a busy
state while the remote processor accesses and processes the read request.
Therefore, to speed up processing flow during reassembly, the CN8236
uses only control and status writes across the PCI bus between host and
local systems.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
Figure
5-12: two in the
28236-DSH-001-B
CN8236