cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 304

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 ATM UTOPIA Interface
12.6 UTOPIA Level 1 Mode Octet Handshake Timing
Figure 12-4. Receive Timing in UTOPIA Level 1 Mode with Octet Handshake
12-14
RXD/RXPAR
NOTE(S):
(1)
RXCLAV
RXCLK
RxEN* goes inactive only if there is no room for another octet in the receive FIFO buffer.
RXEN*
H1
H2
12.6 UTOPIA Level 1 Mode Octet Handshake Timing
If low, the UTOPIA_MODE bit in the CONFIG0 register selects octet-level
handshaking. Received data is latched from the RxData[15:0] and RxPar lines on
the rising edge of RxClk after RxEN* is sampled active (see
odd parity computed over the RxData[15:0] lines is compared to the RxPar input.
If in error, FR_PAR_ERR in the HOST_ISTAT0/LP_ISTAT0 registers is set. Data
is discarded upon a parity if the RSM_PHALT bit in the RSM_CTRL register is
set to a logic high, and the reassembly coprocessor halts.
physical layer FIFO buffer empty signal. When it is active, no data is present in
the physical receive FIFO buffer. The physical layer device sets RxClav inactive
when it has an octet to transfer. The CN8236 sets RxEN* to a logic low if it can
accept an octet in the next clock cycle. The FR_RMODE bit in the CONFIG0
register should be set to a logic low in this mode.
The RxSOC signals the start of cell to the CN8236. The RxClav input is the
H3
(1)
Mindspeed Technologies
X
H4
X
ATM ServiceSAR Plus with xBR Traffic Management
H5
™
***
P48
H1
Figure
28236-DSH-001-B
H2
12-4). The
H3
CN8236
8236_073