cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 305

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 12-5. Transmit Timing in UTOPIA Level 1 Mode with Octet Handshake
28236-DSH-001-B
TXD/TXPAR
NOTE(S):
(1)
(2)
TXSOC
TXCLAV
TXCLK
TxEN* goes active of TxClav is inactive at previous rising clock edge and a complete cell in the transmit FIFO buffer.
TxEN* goes inactive one to four clock cycles after TxClav goes active.
TXEN*
X
(1)
H1
TxEN* is asserted. TxEN* is only asserted when there is data in the CN8236
transmit FIFO buffer. Simultaneously, odd parity computed over the
TxData[15:0] lines is driven on to the TxPar output. The TxSOC line is driven by
the framer device to indicate start of cell. If the TxClav input is asserted by the
framer device, the framer device is full and can accept only one to four more
octets. (See
output, which is a 50% duty cycle clock derived by dividing the CLK2X input by
three.
Transmit data is driven on TxData[15:0] on the rising edge of TxClk when
In UTOPIA mode, the TxClk input can be connected to the CN8236 CLKD3
***
Mindspeed Technologies
Figure
P44
12-5.)
P45
P46
P47
12.6 UTOPIA Level 1 Mode Octet Handshake Timing
(2)
™
X
X
12.0 ATM UTOPIA Interface
P48
H1
H2
12-15
8236_074