cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 72

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

3.0 Host Interface
3.2 Multiple Client Architecture
Figure 3-2. Peer-to-Peer vs. Centralized Memory Data Transfers
3.2.5 Local Processor Clients
Figure 3-3. Out-of-Band Control Architecture
3-4
Frame I/O
Peer
PCI
PCI Card
System
Host
Memory
Peer
PCI BUS
The CN8236 supports limited bandwidth SAR-shared memory segmentation and
reassembly. Any peer can use the local processor port instead of the PCI bus for
data traffic, control, and status. Hosts can use SAR-shared memory for control
and status, but transfer data across the PCI bus. This out-of-band. control
configuration diverts control overhead from the PCI bus, lessening the burden of
ATM’s high throughput and robust management requirements on the host system.
Figure 3-3
Local Processor Port
Frame I/O
Host
PCI
PCI Motherboard
Mindspeed Technologies
PCI BUS
shows an out-of-band control architecture.
2
Subsystem
CN8236
Centralized
1
Memory
ATM ServiceSAR Plus with xBR Traffic Management
LEGEND:
1
LEGEND:
™
#
#
ATM
NETWORK
CN8236
Data Flow
Host Control/Status Flow
PCI Transaction
Peer-to-Peer Transaction
Centralized Memory Transaction
Data Buffer
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