cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 64

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Table 2-1. Hardware Signal Definitions (2 of 6)
2-30
HPERR*
HSERR*
HCLK
HRST*
PCI5V
HSWITCH*
HLED*
HENUM*
HFIFORD[5:0]
HFIFOWR[5:0]
FRCFG[1:0]
TxData[15:0]
TxAddr[4:0]
TxPar
TxSOC
Pin Label
Bus Parity Error
System Error
Bus Clock
System Reset
Bus Signalling
LED Power
ENUM#
AALx FIFO Read
Strobes
AALx FIFO Write
Strobes
Framer Configuration
Transmit Data
Transmit Address
Transmit Data Parity
Transmit Cell Marker
Switch Indicator
Signal Name
Mindspeed Technologies
I/O
OD
OD
OD
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
Indicates a system error or a parity error on the HAD[31:0]
Driven asserted by the CN8236 (as a bus slave) or by a target
addressed by the CN8236 when it acts as a bus master to
indicate a parity error on the HAD[31:0] and HC/BE[3:0]*
lines. It is asserted when the CN8236 is a bus slave or
sampled when the CN8236 is a bus master on the second
clock edge after a valid data phase. The CN8236 drives the
HPERR* line only when acting as a slave.
and HC/BE[3:0]* lines during an address phase. This pin is
handled in the same way as HPERR*, and is only driven by the
CN8236 when it acts as a bus slave.
Supplies the PCI bus clock signal.
Performs a hardware reset of the CN8236 and associated
peripherals when asserted. Must be asserted for 16 cycles of
HCLK.
Must be tied high. This PAD has an internal pullup resister to
VDD.
Logic low means switch locked, logic high means switch
unlocked. Signal pulled up internally. Compact PCI Hot Swap
Signal.
12 mA open drain. Logic low turns on LED. Compact PCI Hot
Swap Signal.
8 mA open drain. Compact PCI Hot Swap Signal.
AALx ingress FIFO buffer read strobe. This signal is edge-
detected inside the SAR so no setup/hold time required.
Signals pulled up internally.
AALx egress FIFO buffer write strobe. This signal is edge-
detected inside the SAR so no setup/hold time required.
Signals pulled up internally.
Configuration pins FRCFG[1,0] determine what framer
interface the CN8236 supports.
00 = Reserved; do not use
01 = UTOPIA interface
10 = Slave UTOPIA interface
11 = Reserved; do not use
Carries outgoing data bytes to the framer chip in all framer
modes (8 mA drive).
Outputs the 8-bit odd parity computed over the TxData[15:0]
lines in all framer modes (8 mA drive).
In both UTOPIA and slave UTOPIA modes, the TxSOC line is
asserted by the CN8236 when the starting byte of a 53-byte
cell is being output. (aka TxMark)
UTOPIA Transmit address (8 mA drive).
ATM ServiceSAR Plus with xBR Traffic Management
™
Definition
28236-DSH-001-B
CN8236