cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 257

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
device), and to a future second Mindspeed PHY device. This mapping is only
valid when the PROCMODE input pin is pulled high, indicating standalone
operation with no local processor present.
operation. When PROCMODE is logic low and the local processor is present,
addresses 0x1FFh through 0xFFFh are available for general use and are mapped
to MCS[0]*.
that the memory controller uses to access the SRAM. A logic 0 indicates 0 wait
state or single-cycle memory, while a logic 1 indicates one wait state or two-cycle
memory. The power-on default is MEMCTRL = 1, selecting one wait state or
two-cycle memory accesses.
processor follow the convention for SRAM accesses; that is, either 0 or 1 wait
state, depending on MEMCTRL programming. Subsequently, the local processor
sees no functional timing differences between accesses to registers or SRAM. The
internal register accesses from the PCI slave interface are always 0 wait state.
When the CN8236 decodes a PCI slave read to its address space, the CN8236
performs a prefetch of four subsequent (contiguous) word locations.
speed and the amount and organization of the memory. The required system clock
speed for a given application is dependent on the physical line rate, number of
VCCs, and the percentage of idle cells versus assigned cells. Memory access
times and other requirements are specified at three typical implementations of
one, two, and four banks of by_8 SRAM. In terms of address bus loading, one
bank of by_8 SRAM equals one-half bank of by_16 or two banks of by_4. In this
way, the system designer can choose the appropriate SRAM characteristics to suit
the amount of memory and organization required for the application. (See
Chapter 16.0
The memory map contains space allocated to the RS825x (physical layer
The MEMCTRL bit in the CONFIG0 register selects the number of wait states
Accesses made to the control registers and internal SRAM by the local
SRAM access time requirements are directly proportional to the system clock
Mindspeed Technologies
for timing information.)
™
Section 10.6
9.2 Memory Bank Characteristics
9.0 Local Memory Interface
details standalone
9-5