zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 99

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7.3
I²C Address 0BE, CPU Address:h602)
Accessed by CPU and I²C (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
FEN – Feature Register
Statistic Counter
0 – Disable (Default)
1 – Enable (all ports)
When statistic counter is enable, an interrupt control frame is generated to
the CPU, every time a counter wraps around. This feature requires an
external CPU.
0
Support DS EF Code.
0 – Disable (Default)
1 – Enable (all ports)
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
Enable VLAN ID hashing
0 – Disable (Default)
1 – Enable
Disable IP Multicast Suppor t
0 – Enable IP Multicast Support (Must also set PVMODE[6]=1)
1 – Disable IP Multicast Support (Default)
When enable, IGMP packets are identified by search engine and are passed
to the CPU for processing. IP multicast packets are forwarded to the IP
multicast group members according to the VLAN port mapping table.
Report to CPU
0 – Disable (Default)
1 – Enable
When disable new VLAN port association report, new MAC address report or
aging reports are disable for all ports. When enable, register SE_OPMODE is
used to enable/disable selectively each function.
MII Management State Machine
0: Enable (Default)
1: Disable
This bit must be set so that there is no contention on the MDIO bus between
MII Management state machine and MIIC & MIID PHY register accesses.
MCT Link List structure
0 – Enable (Default)
1 – Disable
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ZL50405
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Data Sheet