zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 75

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.2
12.3.2.1
I²C Address 028; CPU Address:h100
Accessed by CPU and I²C (R/W)
12.3.2.2
I²C Address 029; CPU Address:h101
Accessed by CPU and I²C (R/W)
12.3.2.3
I²C Address 02A, CPU Address:h102
Accessed by CPU and I²C (R/W)
In Port Based VLAN Mode
This register indicates the legal egress ports. A “1” on bit 3 means that the packet can be sent to port 3. A “0” on bit
3 means that any packet destined to port 3 will be discarded. This register works with registers 1 to form a 10 bit
mask to all egress ports.
In Tag based VLAN Mode
This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form a default VLAN tag.
If the received packet is untagged, then the packet is classified with the default VLAN tag. If the received packet has
a VLAN ID of 0, then PVID is used to replace the packet’s VLAN ID.
12.3.2.4
I²C Address h34, CPU Address:h103
Accessed by CPU and I²C (R/W)
In Port based VLAN Mode
Bits [7:0]:
Bits [7:0]:
(Group 1 Address) VLAN Group
Bits [3:0]:
Bit[7:4]:
Bits [7:0]:
Bits [1:0]:
Bits [7:2]:
AVTCL – VLAN Type Code Register Low
AVTCH – VLAN Type Code Register High
PVMAP00_0 – Port 0 Configuration Register 0
PVMAP00_1 – Port 0 Configuration Register 1
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0x00)
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81)
VLAN Mask for port 0 (Default 0xF)
Reserved (Default 0xF)
PVID [7:0] (Default is 0xFF)
VLAN Mask for ports 9 to 8 (Default 0x3)
Reserved (Default 0x3F)
Zarlink Semiconductor Inc.
ZL50405
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Data Sheet