zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 82

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.4.8
CPU Address:h310
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00)
12.3.4.9
INTP_MASK1 CPU Address:h311 (Ports 2,3)
INTP_MASK4 CPU Address:h314 (Port CPU,MMAC)
12.3.4.10
CPU Address:h323
Accessed by CPU (RW)
Select which receive queue is being used by the CPU port.
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]
-
-
Bit [0]:
Bit [1]:
Bit [2]:
Bits [6:3]:
Bit [7]:
1: Mask the interrupt
0: Unmask the interrupt (Default)
INTP_MASK0 – Interrupt Mask for MAC Port 0,1
INTP_MASKn – Interrupt Mask for MAC Ports 2~9 Registers
Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources
Port 0 link change mask
Port 0 module detect mask
Reserved
Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources.
Port 1 link change mask
Port 1 module detect mask
Reserved
RQS – Receive Queue Select
Bit [0]:
Bit [1]:
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read
Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read
Reserved
Device Timeout Detected interrupt
Select Queue 0
0: Not selected (Default)
1: Selected
Select Queue 1
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ZL50405
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Data Sheet