zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 62

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zl50405

Manufacturer Part Number
zl50405
Description
Managed5-port 10/100 M Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
USER_PORT3:2_
PRIORITY
USER_PORT5:4_
PRIORITY
USER_PORT7:6_
PRI ORITY
USER_PORT_
ENABLE[7:0]
USER_PORT_
FORCE_DISCARD[7:0]
RLOWL
RLOWH
RHIGHL
RHIGHH
RPRIORITY
6. MISC Configuration Register
MII_OP0
MII_OP1
FEN
MIIC0
MIIC1
MIIC2
MIIC3
MIID0
MIID1
USD
DEVICE
SUM
LHBTimer
LHBReg0
LHBReg1
Register
User Define Logic Port 2
and 3 Priority
User Define Logic Port 4
and 5 Priority
User Define Logic Port 6
and 7 Priority
User Define Logic Port 0 To
7 Enable
User Define Logic Port 0 To
7 Force Discard Enable
User Define Range Low Bit
[7:0]
User Define Range Low Bit
[15:8]
User Define Range High
Bit [7:0]
User Define Range High
Bit [15:8]
User Define Range Priority
MII Register Option 0
MII Register Option 1
Feature Registers
MII Command Register 0
MII Command Register 1
MII Command Register 2
MII Command Register 3
MII Data Register 0
MII Data Register 1
One micro second divider
Device id and test
EEPROM Checksum
Register
Link heart beat time out
timer
LHB control field value[7:0]
LHB control field value
[15:8]
Table 13 - Register Description (continued)
Description
Zarlink Semiconductor Inc.
ZL50405
62
CPU Addr
(Hex)
5A0
5A1
5A2
5A3
5A4
60A
60B
591
592
593
594
595
600
601
602
603
604
605
606
607
608
609
610
612
611
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
(Hex)
Addr
0AE
0BC
0BD
0BE
0A3
0A4
0A5
0A6
0A7
0AF
0B0
0B1
0B2
0FF
NA
NA
I²C
NA
NA
NA
NA
NA
NA
NA
NA
NA
Default
000
000
000
000
000
000
000
000
000
000
000
000
010
000
000
000
000
000
002
000
000
000
000
NA
NA
Data Sheet
Notes

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