zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 115

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

CPU address ECB
Accessed by CPU (RO)
CPU address ECC
Accessed by CPU (RO)
CPU address ECD
Accessed by CPU (RO)
12.3.11
12.3.11.1
CPU Address: hF00
Accessed by CPU (R/W)
Bits [5:0]
Bits [7:6]
Bits [1:0]
Bits [3:2]
Bit [4]
Bits [7:5]
Bits [4:0]
Bit [5]
Bits [7:6]
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
(Group F Address) CPU Access Group
GCR - Global Control Register
Rls_count[6:2]
If 1, then It is multicast packet.
Rls_src_port[1:0[
Rls_tail_ptr[14:9]
Rls_count[1:0]
Rls_src_port[3:2]
Class[1:0]
This release request is from QM directly.
Entries count in release FIFO, 0 means FIFO is empty
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Zarlink Semiconductor Inc.
ZL50405
115
Data Sheet