zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 41

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a
Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling
Queue (TxSch Q) or Queues. There are 2 TxSch Q for each RMAC port (and 4 per MMAC and CPU ports), one
for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast,
or adding an entry to a physical queue if multicast.
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of
the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service).
(The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The
older HOL between the two queues goes first.
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the
destination port.
6.2
This section briefly describes the functions of each of the modules of the ZL50405 frame engine.
6.2.1
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure.
The FCB manager is also responsible for enforcing buffer reservations and limits that will be used for QoS control
and source port flow control. The default values can be determined by referring to Section 7.6 on page 44. The
frame buffer is managed in a 128bytes block unit. During initialization, this block will link all the available blocks in a
free buffer list. When each port is ready to receive, this module hands the buffer handle to each requesting port.
The FCB manager will also link the released buffer back into the free buffer list.
The maximum buffer size can be increased from the standard 1518 bytes (1522 with VLAN tag) to up to 4 K bytes.
This is done using BUF_LIMIT, and is enabled on a per port basis via bit [1] in ECR3Pn. See Buffer Allocation
application note, ZLAN-47, for more information.
6.2.2
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch
request.
6.2.3
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
6.2.4
First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this
information, makes the frame dropping decision after receiving a switch response. The dropping decision includes
the head-of-link blocking avoidance if the source port is not flow control enabled. If the decision is not to drop, the
TxQ manager links the unicast frame’s FCB to the correct per-port-per-class TxQ and updates the FCB information.
If multicast, the TxQ manager writes to the multicast queue for that port and class and also update the FCB
information including the duplicate count for this multicast frame. The TxQ manager can also trigger source port
flow control for the incoming frame’s source if that port is flow control enabled. Second, the TxQ manager handles
transmission scheduling; it schedules transmission among the queues representing different classes for a port.
Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port
control module. The detail of the QoS decision guideline is described in chapter 5.
Frame Engine Details
FCB Manager
Rx Interface
RxDMA
TxQ Manager
Zarlink Semiconductor Inc.
ZL50405
41
Data Sheet