zl50405 Zarlink Semiconductor, zl50405 Datasheet
zl50405
Related parts for zl50405
zl50405 Summary of contents
Page 1
... Rate Control (both ingress and egress) • Bandwidth rationing, Bandwidth on demand, ZL50405 MII 5-Port 10/100M Ethernet Switch RMII / MII / GPSI Quad 10/100 PHY Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. ZL50405 Data Sheet January 2005 208 Pin LBGA -40GC to +85GC 2 C EEPROM 10/100 PHY ...
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... Backpressure flow control for Half Duplex ports • Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-In Self Test for internal SRAM • IEEE-1149.1 (JTAG) test port ZL50405 2 Zarlink Semiconductor Inc. Data Sheet ...
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... The ZL50405 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. The ZL50405 supports groups of port trunking/load sharing. Each group can contain ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth ...
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... Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 MAC Address Filtering 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ZL50405 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.4 JTAG Test Clock (TCK) speed requirements 10.2 Clock Generation 10.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.3 Ethernet Interface Clocks 11.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 IEEE 802.3 HUB Management (RFC 1516 11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1.3 FCSErrors 11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ZL50405 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... BUF_LIMIT – Frame Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.1.6 FCC – Flow Control Grant Period 12.3.2 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.1 AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.2 AVTCH – VLAN Type Code Register High 12.3.2.3 PVMAP00_0 – Port 0 Configuration Register ZL50405 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... RDRC1 – WRED Rate Control 12.3.6.7 RDRC2 – WRED Rate Control 12.3.6.8 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.9 C1RS – Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.10 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.11 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.6.12 AVPML – VLAN Tag Priority Map ZL50405 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.1 MIRROR CONTROL – Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0 100 12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0 100 12.3.8.4 RMAC_MIRROR0 – RMAC Mirror 100 ZL50405 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...
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... DA – Dead or Alive Register 114 13.0 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1 Absolute Maximum Ratings 115 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ZL50405 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...
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... I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4.7 Serial Interface Setup Timing 123 13.4.8 JTAG (IEEE 1149.1-2001 124 14.0 Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.2 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.5 November 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ZL50405 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...
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... M2_RX M2_C M2_TX M3_RX M3_C 1.2 Power and Ground Distribution G7-10, H7-10, J7-10, K7-10 D5, D12, E4, E13, M4, M13, N5 D9, H4, H13, N7 ZL50405 P_DAT P_DAT P_DAT P_DAT P_DAT A11 P_DAT P_DAT P_DAT P_DAT P_DAT A10 ...
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... N4, P4, R4, T4, N1, M[3:0]_RXD[3:0] Input P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1 T5, T2, L1, H1 M[3:0]_CRS_DV Input ZL50405 Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Input & Output signal with Tri-State driver Weak internal pull-up (nominal 100K ohm) (refer to Section 1.4 on page 17 as some internal ...
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... M9_TXEN A15 M9_MTXCLK Test Interface C11, C10, D10, C9, TSTOUT[15:0] C8, D8, C7, D7, C6, C5, C4, D4, C3, D3, C2, D2 ZL50405 I/O Output, slew Ports [3:0] – Transmit Enable This pin also serves as a bootstrap pin. Output, slew Ports [3:0] – Transmit Data Bit [3:0] Input Ports[3:0] – Collision with pull-down Input or Output Ports[3:0] – ...
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... V SS K7-10 Misc. D1 RESIN# C1 RESETOUT# F1 M_MDC F2 M_MDIO R7 M_CLK A13 REF_CLK ZL50405 I/O Input JTAG - Test Data In with pull-up Input JTAG - Test Reset with pull-up Input JTAG - Test Clock with pull-up Input JTAG - Test Mode State with pull-up Output JTAG - Test Data Out Input Scan Enable ...
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... B15, A14 Bootstrap Pins (1= pull-up 0= pull-down) (See “Bootstrap Options” on page 20) D2 TSTOUT[0] C3, D3, C2 TSTOUT[3:1] C5, C4, D4 TSTOUT[6:4] C6 TSTOUT[7] ZL50405 I/O N/A Reserved. Leave unconnected. 1 Input (Reset Only) Enable Debounce of STROBE signal Pullup – Enabled Pulldown - Disabled Input (Reset Only) Management interface operation mode: 000 – ...
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... C11, C10, D10 TSTOUT[15:13] R5, R2, L2, H2 M[3:0]_TXEN 1. External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10 K for pull-ups and 1 K for pull-downs. ZL50405 I/O Input (Reset Only) Manufacturing Option. Must be pulled up. Must be externally pulled-up Input (Reset Only) Module Detect Pullup: Enable ...
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... Signal Mapping and Internal pull-up/Down Configuration The ZL50405 Fast Ethernet access ports (0-3) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the “Ball Signal Description Table” on page 12. It also specifies whether the internal pull-up/down resistor is present for each pin in the specific operating mode ...
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... The ZL50405 Fast Ethernet uplink port (port 9) supports 1 interface option: MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. Fast Ethernet Uplink Port ...
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... The ZL50405 CPU access support 5 interface options 16-bit parallel, serial+MII (port 8), serial only, and unmanaged serial (with optional EEPROM). The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. ...
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... Also, in unmanaged mode, an optional I the device at power-up or reset. TSTOUT[7] selects the EEPROM option. The ZL50405 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[3:0]_TXEN (ports 0-3) are used to specify the module type to support multiple ethernet interfaces during module hotswap ...
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... Default Switch Configuration and Initialization Sequence The ZL50405 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic MAC address learning. In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be changed using the optional EEPROM. • ...
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... DiffServ EF code support disabled • No VLAN ID hashing • Per-port Defaults • FE Ports - Link heart beat disabled • CPU Port - 100M/Full Duplex/Flow Control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers ZL50405 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M), Reverse MII, or Reverse GPSI (only for 10M). The RMAC of the ZL50405 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...
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... Frame Engine (FE) and the external physical device (PHY). The MMAC implements an MII interface. The MMAC of the ZL50405 device meets the IEEE 802.3 specification able to operate in 10 M/100 M either Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit upon collision for total transmissions ...
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... Heartbeat Packet Generation and Response The ZL50405 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time period reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link ...
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... The CPU interface provides for easy and effective management of the switching system. Figure 3 on page 27 provides an overview of the 8/16-bit interface. Figure 4 on page 28 provides an overview of the SSI interface. Figure 5 on page 29 provides an overview of the SSI+MII interface. ZL50405 ISA Interface Serial 16-bit ...
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... Reg (Addr = 0) 8-bit only ) (Addr = 2) 16-bit Address 8-bit Data Bus Internal Registers Inderect Access Figure 3 - Overview of the 8/16-bit Interface ZL50405 Processor 3-bit Address 8/16-bit Data Bus Bus Address I/O Data MUX Command/ CPU Frame Reg Interrupt Reg Status Reg (Addr = 3) (Addr = 5) ...
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... Address CPU f rame Internal Transmit CPU f rame Registers Receiv e Inderect FIFO Access Figure 4 - Overview of the SSI Interface Zarlink Semiconductor Inc. ZL50405 Serial In Strobe Interrupt 16-bit Data Bus INT I/O Data MUX Command/ Control Command Interrupt Reg Status Reg 1 Reg (Addr = 5) ...
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... Register Configuration The ZL50405 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers, as follows: • ...
Page 30
... To transmit a frame from the CPU with MII interface: • ZL50405 acts as a PHY to provide receive clock (RXCLK) to CPU so the CPU will depend on this receive clock to send packets to ZL50405 • ZL50405 has the ability to halt the receive clock if the receive FIFO of ZL50405 is overflow. Transmitting from CPU to ZL50405 will resume once the receive FIFO of ZL50405 is no longer overflow • ...
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... I C Interface The I²C interface serves the function of configuring the ZL50405 at boot time. The master is the ZL50405, and the slave is the EEPROM memory. The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch ...
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... I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time bits are used to allow up to eight ZL50405 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. ...
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... Data to be written or read back Write operation can be aborted in the middle by sending an ABORT pulse to the ZL50405. Read operation can only be aborted before issuing the read command to the ZL50405. A START command is detected when DATAIN is sampled high when STROBE- rise and DATAIN is sampled low when STROBE- fall ...
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... RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the MMAC and CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the ZL50405 34 Zarlink Semiconductor Inc. ...
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... Basic Flow Shortly after a frame enters the ZL50405 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...
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... Broadcast, unknown unicast or unknown multicast MAC address can also be filter on per VLAN basis. MAC address filtering allows the ZL50405 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem ...
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... Extensive core QoS mechanisms are built into the ZL50405 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the ZL50405, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class ...
Page 38
... Definition” on page 59). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50405 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50405 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...
Page 39
... In addition, coordinating VLAN IDs across multiple switches enables VLANs to extend to multiple switches VLANs are supported in the ZL50405. When tag-based VLAN is enabled, each MAC address is learned with it associated VLAN. ...
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... IEEE 802.1Q Tag TPID = 0x8100 * Provider Tag TPID = Configurable on per device basis The value of the TPID of the Provider VLAN tag is not assigned in the IEEE 802.1ad standard. The ZL50405 provides a global configurable TPID but only supports the Extreme EtherType TPID (i.e. the stacked VLAN tag cannot equal 0x81-00) ...
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... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50405 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. ...
Page 42
... A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high ZL50405 Low Drop Probability (low-drop) Apps: phone calls, circuit emulation ...
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... This provides per-class bandwidth partitioning with granular within 2%. In WFQ mode, though we do not assure frame latency, the ZL50405 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. ...
Page 44
... As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the ZL50405, its destination port and class are as yet unknown, and so the decision to drop or not needs to ZL50405 Px > ...
Page 45
... If the output queue reach the UCC (unicast congest control) and the shared buffer has run out, the frame will be dropped by b%. If the output queue reach the UCC and the source port reservation is lower than the buffer low threshold, the frame will be dropped. All the dropping functions are disabled if the source port is flow control capable. ZL50405 Temporary reservation R R ...
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... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50405’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...
Page 47
... On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50405 to reset the timeout counter ignored otherwise (i.e. not passed on within the system). ...
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... VLAN. When a multicast packet is sent in from port 3, the ZL50405 select port 0,1,2,3,4,5 and 6 as potential destination based on the VLAN. Then port 3 and 4 are removed because they belong to the source port group (trunk group 1). Two ports from trunk group 0 will be removed based on the hash key ...
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... Clocks 10.1 Clock Requirements 10.1.1 System Clock (SCLK) speed requirement SCLK is the primary clock for the ZL50405 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 1-5 ports 10/100M 10.1.2 RMAC Reference Clock (M_CLK) speed requirement M_CLK MHz clock used for the RMAC ports (ports 0-3) and CPU port (port 8). ...
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... Hardware Statistics Counters List ZL50405 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager) ...
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... Oversize Frames B[15] 9-U Frames with Length Between 128-255 Bytes B[16] A-l B[17] A-u Frames with Length Between 256-511 Bytes B[18] B-l Frames with Length Between 512-1023 Bytes Frames with Length Between 1024-1528 Bytes B[19] B-u Fragments B[20] C-l Alignment Error B[21] C-U1 Undersize Frames B[22] C-U CRC B[23] D-l Short Event B[24] D-u Collision B[25] E-l Drop B[26] E-u ZL50405 51 Zarlink Semiconductor Inc. Data Sheet ...
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... IEEE 802.3 HUB Management (RFC 1516) 11.2.1 Event Counters 11.2.1.1 ReadableOctet Counts number of bytes (i.e., octets) contained in good valid frames received. Frame size: No FCS (i.e. checksum) error No collisions ZL50405 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) 52 Zarlink Semiconductor Inc. Data Sheet ...
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... FrameTooLongs Counts number of frames received with size exceeding the maximum allowable frame size. Frame size: FCS error: Framing error: No collisions ZL50405 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) > 64 bytes, < 1522 bytes if VLAN Tagged; ...
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... Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: Events are also counted by collision counter 11.2.1.10 VeryLongEvents Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3). Frame size: ZL50405 < 10 bytes don’t care don’t care > 10 bytes, < 64 bytes don’t care don’ ...
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... InDiscards Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process. 11.3.1.4 DelayExceededDiscards Counts number of frames discarded due to excessive transmit delay through the bridge. 11.3.1.5 MtuExceededDiscards Counts number of frames discarded due to excessive size. ZL50405 55 Zarlink Semiconductor Inc. Data Sheet ...
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... No collisions: 11.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions ZL50405 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) < 64 bytes, 56 Zarlink Semiconductor Inc. Data Sheet ...
Page 57
... Jabbers Counts number of frames received with size exceeding maximum frame size and with bad FCS. Frame size: Framing error No collisions ZL50405 > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’t care < ...
Page 58
... Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50405 has other statistics counters for its own purposes. We have two counters for flow control – one counting the number of flow control frames received, and another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “ ...
Page 59
... Register Definition 12.1 ZL50405 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..3,8,9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 for Port n ECR4Pn Port Control Register 4 for Port n BUF_LIMIT Frame Buffer Limit ...
Page 60
... MAC Address Aging Time High SE_OPMODE Search Engine Operating Mode 5. Global QOS Control QOSC QOS Control UCC Unicast Congestion Control MCC Multicast Congestion Control Table 13 - Register Description (continued) ZL50405 CPU Addr Description (Hex) 229+2n 300 301 302 303 304 305 306 310+n 323 ...
Page 61
... Force Discard Enable USER_PORTn_LOW User Define Logical Port n Low USER_PORTn_HIGH User Define Logical Port n High USER_PORT1:0_ User Define Logic Port 0 PRIORITY and 1 Priority Table 13 - Register Description (continued) ZL50405 CPU Addr Description (Hex) 512 513 514 515 518 519 51A 51B 530 ...
Page 62
... Device id and test SUM EEPROM Checksum Register LHBTimer Link heart beat time out timer LHBReg0 LHB control field value[7:0] LHBReg1 LHB control field value [15:8] Table 13 - Register Description (continued) ZL50405 CPU Addr Description (Hex) 591 592 593 594 595 5A0 5A1 5A2 5A3 ...
Page 63
... Address 3 MIRROR_SRC_MAC4 Mirror Source MAC Address 4 MIRROR_SRC_MAC5 Mirror Source MAC Address 5 MIRROR_CONTROL Port Mirror Control Register RMAC_MIRROR0 RMAC Mirror 0 RMAC_MIRROR1 RMAC Mirror 1 Table 13 - Register Description (continued) ZL50405 CPU Addr Description (Hex) 613 614 620 621 622 700 701 702 703 704 ...
Page 64
... MASK3 MASK Timeout 3 MASK4 MASK Timeout 4 BOOTSTRAP[2:0] BOOTSTRAP Read Back PRTFSMSTn Ethernet Port n Status Read Back PRTQOSSTn RMAC Port n QOS and Queue Status Table 13 - Register Description (continued) ZL50405 CPU Addr Description (Hex) 800+n 820+n 840+n 848 849 860+n 868 869 880+n ...
Page 65
... BM_RLSFF_INFO3 Bm_rlsfifo_info[31:24] BM_RLSFF_INFO4 Bm_rlsfifo_info[39:32] BM_RLSFF_INFO5 Fifo_cnt[2:0],Bm_rlsfifo_inf o[44:40] F. System Control GCR Global Control Register DCR Device Control Register DCR1 Device Control Register 1 Table 13 - Register Description (continued) ZL50405 CPU Addr Description (Hex) EA8 EA9 EAA EAB EAC EAD EB0+n EBA EBB EBC EBD ...
Page 66
... Frame status (Frame size, Source port #, VLAN tag) Frame Data (size should be in multiple of 8-byte) 12.2.5 COMMAND&STATUS Register • CPU interface commands and status (8 bits) • Address = 4 (read/write) • When the CPU writes to this register ZL50405 CPU Addr Description (Hex) F03 F04 FFF 66 Zarlink Semiconductor Inc. Data Sheet I² ...
Page 67
... Bit [2]: Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read Bits [6:3]: Reserved Bit [7]: Device Timeout Detected interrupt Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it. ZL50405 67 Zarlink Semiconductor Inc. Data Sheet ...
Page 68
... ECR1Pn[2:0] for configuration). Hardware will still poll PHY for link status Force Link Down Disable the port. Hardware does not talk to PHY Force Link Up The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control) setup. Hardware does not talk to PHY. ZL50405 68 Zarlink Semiconductor Inc. Data Sheet ...
Page 69
... Enable Asymmetric flow control When this bit is set and flow control is on (bit [0] = 0), the device does not send out flow control frames, but it’s receiver interprets and processes flow control frames. ZL50405 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. ...
Page 70
... Bit [5] Do not change VLAN tag. This overrides PVMAPnn_3 bit [2]. If this bit is set, no tag will be replaced nor removed. 0: Disable (Default) 1: Enable ZL50405 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 70 Zarlink Semiconductor Inc. ...
Page 71
... Bits [7:6] Security Enable. The ZL50405 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. ...
Page 72
... MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Link Heart Beat Receive 0: Disable (Default). Also clears all MAC LHB status. 1: Enable Bit [7]: Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing. ZL50405 72 Zarlink Semiconductor Inc. Data Sheet ...
Page 73
... Reserved Bit [1]: Enable RXCLK output. Active high 0: Disable (Default) 1: M9_RXCLK pin becomes output in MII mode Note: To configure port 9 with the device providing the interface clocks, you need to tie M9_RXCLK to M9_MTXCLK externally as M9_MTXCLK is not a bidirectional clock. ZL50405 73 Zarlink Semiconductor Inc. Data Sheet ...
Page 74
... CPU Address:h036 Accessed by CPU (R/W) Bits [6:0]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40) Bit [7]: Reserved 12.3.1.6 FCC – Flow Control Grant Period CPU Address:h037 Accessed by CPU (R/W) Bits [2:0]: Flow Control Grant Period (Default 0x3) Bits [7:3]: Reserved ZL50405 74 Zarlink Semiconductor Inc. Data Sheet ...
Page 75
... VLAN then PVID is used to replace the packet’s VLAN ID. 12.3.2.4 PVMAP00_1 – Port 0 Configuration Register 1 I²C Address h34, CPU Address:h103 Accessed by CPU and I²C (R/W) In Port based VLAN Mode Bits [1:0]: VLAN Mask for ports (Default 0x3) Bits [7:2]: Reserved (Default 0x3F) ZL50405 75 Zarlink Semiconductor Inc. Data Sheet ...
Page 76
... Force untag out (VLAN tagging is based on IEEE 802.1Q rule Disable (Default Force untagged output. All packets transmitted from this port are untagged. This bit is used when this port is connected to legacy equipment that does not support VLAN tagging. ZL50405 76 Zarlink Semiconductor Inc. Data Sheet ...
Page 77
... Enable - Learning disabled port will not receive any flooding packets (Default) 1: Disable Bit [4]: Support MAC address 0 0: MAC address 0 is not learned. (Default) This means packet with destination MAC address 0 is forwarded as unknown destination subjected to unicast to multicast rate control. 1: MAC address 0 is learned. ZL50405 77 Zarlink Semiconductor Inc. Data Sheet ...
Page 78
... Bit [3:0] Port 3-0 bit map of trunk n. (Default 0) 12.3.3.2 TRUNKn_HASH10 – Trunk group n hash result 1/0 destination port number CPU Address:h208+ trunk group) Accessed by CPU (R/W) Bits [3:0] Hash result 0 destination port number (Default 0) Bits [7:4] Hash result 1 destination port number (Default 0) ZL50405 TRUNK0 ...
Page 79
... Ports belonging to the same trunk group should only have a single port set to “1” per entry. The port set to “1” is picked to transmit the multicast frame when the hash value is met. Hash Value =0 Hash Value =1 Hash Value =2 Hash Value =3 Hash Value =4 Hash Value =5 Hash Value =6 Hash Value =7 ZL50405 HASH0-1 HASH0-0 HASH1-1 HASH1-0 HASH2-1 HASH2-0 HASH3-1 HASH3-0 HASH4-1 ...
Page 80
... MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC [5:0], the packet is forwarded to the CPU. The default MAC address is 00-00-00-00-00-00. 12.3.4.1 MAC0 – CPU MAC address byte 0 CPU Address:h300 Accessed by CPU (R/W) Bits [7:0]: Byte 0 (bits [7:0]) of the CPU MAC address (Default 0) ZL50405 MAC3 MAC2 MAC1 MAC0 80 Zarlink Semiconductor Inc. Data Sheet ...
Page 81
... INT_MASK0 – Interrupt Mask CPU Address:h306 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00 Mask the interrupt - 0: Unmask the interrupt (Enable interrupt) (Default) ZL50405 81 Zarlink Semiconductor Inc. Data Sheet ...
Page 82
... INTP_MASK1 CPU Address:h311 (Ports 2,3) INTP_MASK4 CPU Address:h314 (Port CPU,MMAC) 12.3.4.10 RQS – Receive Queue Select CPU Address:h323 Accessed by CPU (RW) Select which receive queue is being used by the CPU port. Bit [0]: Select Queue 0 0: Not selected (Default) 1: Selected Bit [1]: Select Queue 1 ZL50405 82 Zarlink Semiconductor Inc. Data Sheet ...
Page 83
... MAC01, MAC23, and MAC9 registers are used with the MAC0~5 registers to form the CPU MAC address on a per port basis. 12.3.4.13 MAC23 – Increment MAC port 2,3 address CPU Address:h326 Accessed by CPU (RW) Bits [2:0]: Bits [42:40] of Port 2 CPU MAC address Bit [3]: Reserved Bits [6:4]: Bits [42:40] of Port 3 CPU MAC address Bit [7]: Reserved ZL50405 83 Zarlink Semiconductor Inc. Data Sheet ...
Page 84
... Command valid (will be processed on the rising edge of the signal) 12.3.4.16 CPUQINSRPT – CPU Queue Insertion Report CPU Address:h337 Accessed by CPU, (RO) CPU command queue status The command is under processing. Bit [0]: Insertion Fail (May be due to queue full, WRED or filtering) Bit [1]: ZL50405 CQ4 CQ3 CQ2 84 Zarlink Semiconductor Inc. Data Sheet 0 CQ1 CQ0 ...
Page 85
... Accessed by CPU, (R/W) CPU receive queue status Allocate granule to the CPU if set to one. Otherwise, do not allocate any resource. Bit [0]: Read allocated granule (at rising edge only) Bit [1]: Release info valid (will be processed at rising edge only) Bit [2]: ZL50405 15 0 CG1 CG0 CR3 CR2 CR1 ...
Page 86
... AGETIME_LOW – MAC address aging time Low I²C Address h049; CPU Address:h400 Accessed by CPU and I²C (R/W) Used in conjuction with AGETIME_HIGH. The ZL50405 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bits [7:0]: Low byte of the MAC address aging timer (Default 0x5C) 12 ...
Page 87
... C Address h068, CPU Address: 510 2 Accessed by CPU and I C (R/W) Bits [7:0]: Number of frame count. Used for best effort dropping at B% when destination port’s best effort queue reaches UCC threshold and shared pool is all in use. Granularity is 16 granule (Default 0x6) ZL50405 87 Zarlink Semiconductor Inc. Data Sheet ...
Page 88
... Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and destination port best effort queue reaches UCC. Granularity 6.25%. Bits [7:4]: Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%. See Programming QoS Registers application note, ZLAN-42, for more information ZL50405 88 Zarlink Semiconductor Inc. Data Sheet ...
Page 89
... Class 2 FCB Reservation Buffer reservation for class 2. Granularity 16 granules . (Default 0) 12.3.6.11 C3RS – Class 3 Reserve Size I²C Address h077, CPU Address 51B Accessed by CPU and I²C (R/W) Bits [7:0]: Class 3 FCB Reservation Buffer reservation for class 3. Granularity 16 granules . (Default 0) ZL50405 89 Zarlink Semiconductor Inc. Data Sheet ...
Page 90
... VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50405. When the packet goes out it carries the original priority. Bits [2:0]: ...
Page 91
... Accessed by CPU and I²C (R/W) Map TOS field in IP packet into eight level transmit priorities: Bits [1:0]: Priority when the TOS field is 5 (Default 0) Bits [4:2]: Priority when the TOS field is 6 (Default 0) Bits [7:5]: Priority when the TOS field is 7 (Default 0) ZL50405 91 Zarlink Semiconductor Inc. Data Sheet ...
Page 92
... Enable Protocol 0 Force Discard 1 – Enable 0 – Disable Bit [1]: Enable Protocol 1 Force Discard Bit [2]: Enable Protocol 2 Force Discard Bit [3]: Enable Protocol 3 Force Discard Bit [4]: Enable Protocol 4 Force Discard Bit [5]: Enable Protocol 5 Force Discard Bit [6]: Enable Protocol 6 Force Discard ZL50405 92 Zarlink Semiconductor Inc. Data Sheet ...
Page 93
... Enable Protocol 7 Force Discard User Defined Logical Ports and Well Known Ports The ZL50405 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...
Page 94
... Bit [7]: Enable Well Known Port 7 Priority 12.3.6.27 WELL_KNOWN_PORT_FORCE_DISCARD – Well Known Logic Port 0~7 Force Discard I²C Address h0AD, CPU Address 565 Accessed by CPU and I²C (R/W) Bit [0]: Enable Well Known Port 0 Force Discard 1 – Enable 0 – Disable ZL50405 94 Zarlink Semiconductor Inc. Data Sheet ...
Page 95
... USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority I²C Address h0A3, CPU Address 591 Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for logic port 2 Bits [7:4]: Priority setting, transmission + dropping, for logic port 3 (Default 00) ZL50405 7 TCP/UDP Logic Port Low 7 TCP/UDP Logic Port High 95 Zarlink Semiconductor Inc. ...
Page 96
... Enable User Port 7 Priority 12.3.6.34 USER_PORT_FORCE_DISCARD[7:0] – User Define Logic Port 0~7 Force Discard I²C Address h0A7, CPU Address 595 Accessed by CPU and I²C (R/W) Bit [0]: Enable User Port 0 Force Discard 1 – Enable 0 – Disable Bit [1]: Enable User Port 1 Force Discard ZL50405 96 Zarlink Semiconductor Inc. Data Sheet ...
Page 97
... RPRIORITY – User Define Range Priority I²C Address h0B2, CPU Address: 5A4 Accessed by CPU and I²C (R/W) RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [0]: Drop Priority (inclusive only) ZL50405 97 Zarlink Semiconductor Inc. Data Sheet ...
Page 98
... Half duplex flow control by negotiation 12.3.7.2 MII_OP1 – MII Register Option 1 I²C Address 0BD, CPU Address:h601 Accessed by CPU and I²C (R/W) Bits [3:0]: Duplex bit location in vendor specified register Bits [7:4]: Speed bit location in vendor specified register (Default 00) ZL50405 98 Zarlink Semiconductor Inc. Data Sheet ...
Page 99
... Enable (Default) 1: Disable This bit must be set so that there is no contention on the MDIO bus between MII Management state machine and MIIC & MIID PHY register accesses. Bit [7]: MCT Link List structure 0 – Enable (Default) 1 – Disable ZL50405 99 Zarlink Semiconductor Inc. Data Sheet ...
Page 100
... RDY – Data is returned from PHY (Read Only) Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Writing this register will initiate a serial management cycle to the MII management interface. ZL50405 100 Zarlink Semiconductor Inc. Data Sheet ...
Page 101
... DEVICE Mode CPU Address:h60A Accessed by CPU (R/W) Bit [0]: Reserved Bit [1]: CPU Interrupt Polarity 0: Negative Polarity 1: Positive Polarity (Default) Bits [7:2]: Reserved 12.3.7.12 CHECKSUM - EEPROM Checksum I²C Address 0FF, CPU Address:h60B Accessed by CPU and I²C (R/W) Bits [7:0]: Checksum content (Default 0) ZL50405 101 Zarlink Semiconductor Inc. Data Sheet ...
Page 102
... FF $ I²C register = When the ZL50405 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50405 does not start and pin CHECKSUM_OK is set to zero. 12.3.7.13 LHBTimer – Link Heart Beat Timeout Timer CPU Address:h610 Accessed by CPU (R/W) In slot time (512 bit time) ...
Page 103
... MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0~5 CPU Address 706-70B Accessed by CPU (R/W) SRC_MAC5 SRC_MAC4 [47:40] [39:32] (Default 00) (Default 00) 12.3.8.4 RMAC_MIRROR0 – RMAC Mirror 0 CPU Address 710 Accessed by CPU (R/W) Bits [2:0]: Source port to be mirrored ZL50405 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] ...
Page 104
... To disable this function, program U2MR to 0. (Default = 0) Bits [6:4]: Time Base for Unicast to Multicast, Multicast and Broadcast rate control of Port n: (Default = 000) 000 = 100 us 001 = 200 us 010 = 400 us 011 = 800 us 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 12.8 ms Bit [7]: Reserved ZL50405 104 Zarlink Semiconductor Inc. Data Sheet ...
Page 105
... PTH100_CPU – Port CPU Threshold I²C Address h0CB, CPU Address 868 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x3) ZL50405 105 Zarlink Semiconductor Inc. Data Sheet ...
Page 106
... Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED. ZL50405 2 C Address h088, CPU Address 890) ...
Page 107
... NOTE: Device Manufacturing test registers. 12.3.10.1 DTSRL – Test Output Selection CPU Address E00 Accessed by CPU (R/W) Test group selection for testout[7:0]. 12.3.10.2 DTSRM – Test Output Selection CPU Address E01 Accessed by CPU (R/W) Test group selection for testout[15:8]. ZL50405 107 Zarlink Semiconductor Inc. Data Sheet ...
Page 108
... TX FSM NOT idle for 5 sec Bit [0]: TX FIFO control NOT idle for 5 sec Bit [1]: RX SFD detection NOT idle for 5 sec Bit [2]: RXINF NOT idle for 5 sec Bit [3]: PTCTL NOT idle for 5 sec Bit [4]: ZL50405 23 15 BT2 BT1 108 Zarlink Semiconductor Inc. Data Sheet 0 BT0 ...
Page 109
... L2 WRED level Bit [6]: priority queue 2 reach L1 WRED level Bit [7]: priority queue 2 reach L2 WRED level Bit [8]: priority queue 3 reach L1 WRED level Bit [9]: priority queue 3 reach L2 WRED level Bit [10]: priority 0 MC queue full ZL50405 PQSTB PQSTA 109 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 110
... Priority queue 3 reach L1 WRED level Bit [9]: Priority queue 3 reach L2 WRED level Bit [10]: Priority 0 MC queue full Bit [11]: Priority 1 MC queue full Bit [12]: Priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bits [15:14]: Reserved ZL50405 15 PQSTB PQSTA 110 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 111
... CPU Address EB0+n Accessed by CPU (R/W) Bit [0]: Suspend port scheduling (no departure) Bit [1]: Reset queue Bits [4:2]: Reserved Bit [5]: Force out MAC control frame Bit [6]: Force out XOFF flow control frame Bit [7]: Force out XON flow control frame ZL50405 111 Zarlink Semiconductor Inc. Data Sheet ...
Page 112
... MMAC pool 9: shared pool 10: class 1 pool 11: class 2 pool 12: class 3 pool 13: multicast pool 14: cpu pool 15: reserved Bit [4] If this bit is 1, then all the pools are assigned ZL50405 112 Zarlink Semiconductor Inc. Data Sheet ...
Page 113
... Fcb_tail_ptr[14:8]. The tail pointer of free granule link that CPU assigns. Bit [7] Set 1 to write If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. 12.3.10.19 FCB_NUM0, FCB_NUM1 CPU address EC5 Accessed by CPU (R/W) Bits [7:0] Fcb_number[7:0]. The total number of granules that CPU assigns. ZL50405 113 Zarlink Semiconductor Inc. Data Sheet ...
Page 114
... EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from 12.3.10.21 BM_RSLFF_INFO[5:0] CPU address EC8 Accessed by CPU (RO) Bits [7:0] Rls_head_ptr[7:0]. CPU address EC9 Accessed by CPU (RO) Bits [6:0] Rls_head_ptr[14:8]. Bit [7] Rls_tail_ptr[0] CPU address ECA Accessed by CPU (RO) Bits [7:0] Rls_tail_ptr[8:1] ZL50405 114 Zarlink Semiconductor Inc. Data Sheet ...
Page 115
... Write ‘1’ to store configuration into external EEPROM and reset chip Bit [2]: Start BIST (Default = 0) Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is found in the DCR register. Bit [3]: Soft Reset (Default = 0) Write ‘1’ to reset chip ZL50405 115 Zarlink Semiconductor Inc. Data Sheet ...
Page 116
... Busy reading configuration from I²C 0: Not busy (not reading configuration from I²C) Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bits [5:4]: Device Signature 10: ZL50405 device Bits [7:6]: Revision 00: Initial Silicon 01: Second Silicon 12.3.11.3 DCR1 - Device Status Register 1 CPU Address: hF02 Accessed by CPU (RO) Bits [6:0] ...
Page 117
... Auto negotiation disabled 1: Disable 0: Enable Bit [5] Reserved Bit [6] Reserved Bit [7] Module detected (for hot swap purpose module 1: Module detected Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]=’0’), this bit will always be ‘1’. ZL50405 117 Zarlink Semiconductor Inc. Data Sheet ...
Page 118
... Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 13.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50405 - +150 +125 G C +2. +3. +1. + ...
Page 119
... Output Capacitance OUT C I/O Capacitance I/O 6 Thermal resistance with 0 air flow ja 6 Thermal resistance with 1 m/s air flow ja Thermal resistance with 2 m/s air flow 6 ja Thermal resistance between junction and case 6 jc ZL50405 Min. 2.4 2.0 < < OUT CC 119 Zarlink Semiconductor Inc. Data Sheet Typ. Max. ...
Page 120
... R1 Bootstrap Pins Outputs Figure 13 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50405 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising edge of ...
Page 121
... Description Write Cycle Symbol Write Set up Time T Write Active Time T Write Hold Time T Write Recovery time T Data Set Up time T Data Hold time T ZL50405 Activ e Tim e R ecov ery Tim ATA0 H old tim e (SCLK=100 Mhz) (SCLK=50 Mhz) Min ...
Page 122
... Symbol Read Set up Time T Read Active Time T Read Hold Time T Read Recovery time T Data Valid time T Data Invalid time T Table Characteristics - CPU Read Cycle ZL50405 Activ e Tim e R ecov ery Tim ATA0 ...
Page 123
... Figure Characteristics – Reduced Media Independent Interface (RX) Symbol M2 M[3:0]_RXD[1:0] Input Setup Time M3 M[3:0]_RXD[1:0] Input Hold Time M4 M[3:0]_CRS_DV Input Setup Time M5 M[3:0]_CRS_DV Input Hold Time M6 M[3:0]_TXEN Output Delay Time M7 M[3:0]_TXD[1:0] Output Delay Time ZL50405 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Mn_TXD[1:0] M_CLK M2 Mn_RXD M3 M4 Mn_CRS_DV ...
Page 124
... MM3 Mn_RXD[3:0] Input Hold Time MM4 M[9,3:0]_CRS_DV Input Setup Time MM4 M[8]_CRS_DV Input Setup Time MM5 Mn_CRS_DV Input Hold Time MM6 Mn_TXEN Output Delay Time MM7 Mn_TXD[3:0] Output Delay Time ZL50405 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Mn _TXD[3:0] Mn_RXCLK MM2 Mn_RXD[3:0] MM ...
Page 125
... M[3:0]_RXD Input Setup Time SM3 M[3:0]_RXD Input Hold Time SM4 M[3:0]_CRS_DV Input Setup Time SM5 M[3:0]_CRS_DV Input Hold Time SM6 M[3:0]_TXEN Output Delay Time SM7 M[3:0]_TXD Output Delay Time ZL50405 Mn_ TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Mn_RXCLK SM2 Mn_RXD ...
Page 126
... MDIO Input Setup and Hold Timing Figure 22 - MDIO Input Setup and Hold Timing Symbol D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50405 MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 23 - MDIO Output Delay Timing MDC=500 KHz Parameter Min ...
Page 127
... I²C Input Setup Timing Symbol S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50405 SCL S1 SDA Figure 24 - I²C Input Setup Timing SCL S3-max S3-min SDA Figure 25 - I²C Output Delay Timing Parameter Min ...
Page 128
... STROBE Dataout Figure 27 - Serial Interface Output Delay Timing Symbol D1 DATAIN setup time D2 DATAIN hold time D3 DATAOUT output delay time D4 STROBE low time D5 STROBE high time ZL50405 Figure 26 - Serial Interface Setup Timing D3-max D3-min Parameter Min. (ns ...
Page 129
... Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50405 J1 J2 Figure 28 - JTAG Timing Diagram Min. Typ. Max ...
Page 130
... November 2004 • Added section “Default Switch Configuration and Initialization Sequence” on page 21 • Updated CPU timing diagrams to clarify P_A timing • Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable ZL50405 130 Zarlink Semiconductor Inc. Data Sheet ...
Page 131
... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN 14Nov02 DATE APPRD. BOTTOM VIEW b Previous package codes Dimension MIN MAX 1. 0.30 0.50 0.53 REF A2 D 16.90 17.10 E 16.90 17.10 b 0.40 0.60 e 1.00 N 208 Conforms to JEDEC MO-192 Package Code ...
Page 132
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...