zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 39

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming
port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port.
In this example:
•
•
•
5.9.2
The ZL50405 supports the IEEE 802.1q specification for “tagging” frames. The specification defines a way to
coordinate VLANs across multiple switches. In the specification, an additional 4-octet header (or “tag”) is inserted in
a frame after the source MAC address and before the frame type. 12 bits of the tag are used to define the VLAN ID.
Packets are then switched through the network with each ZL50405 simply swapping the incoming tag for an
appropriate forwarding tag rather than processing each packet's contents to determine the path. This approach
minimizes the processing needed once the packet enters the tag-switched network. In addition, coordinating VLAN
IDs across multiple switches enables VLANs to extend to multiple switches.
Up to 4 K VLANs are supported in the ZL50405. When tag-based VLAN is enabled, each MAC address is learned
with it associated VLAN.
See IEEE 802.1Q VLAN Setup application note, ZLAN-51, for more information.
5.9.3
The ZL50405 partially supports VLAN stacking, also called IEEE 802.1Q-in-Q. This technology allows an additional
VLAN tag, called a provider VLAN tag, to be inserted into an existing IEEE 802.1Q tagged Ethernet frame. This
technology has been widely adapted in Metro Ethernet applications since it provides a very cost-effective solution
to transport multiple customers' VLAN across the service provider's MAN/WAN without interfering each other. The
below figure illustrates the IEEE 802.1Q frame and the Q-in-Q frame, where the provider VLAN tag is inserted in
front of the IEEE 802.1Q tag.
Port Registers
Register for Port #0
PVMAP00_0[7:0] to PVMAP00_1[1:0]
Register for Port #1
PVMAP01_0[7:0] to PVMAP01_1[1:0]
Register for Port #2
PVMAP02_0[7:0] to PVMAP02_1[1:0]
…
Register for Port #9
PVMAP09_0[7:0] to PVMAP09_1[1:0]
Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2.
Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2.
Data packets received at port #2 are NOT eligible to be sent to ports 0 and 1.
Tag-Based VLAN
VLAN Stacking (Q-in-Q)
Table 7 - Port-Based VLAN Mapping
Zarlink Semiconductor Inc.
ZL50405
39
9
0
0
0
0
Destination Port Numbers Bit Map
…
1
1
0
0
2
1
1
0
0
0
Data Sheet
0
1
0
0
0