zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 122

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.4.3
Read Set up Time
Read Active Time
Read Hold Time
Read Recovery time
Data Valid time
Data Invalid time
P_A[2:0]
P_C S#
P_R D #
P_D ATA
(to C PU )
Read Cycle
Typical CPU Timing Diagram for a CPU Read Cycle
Description
Figure 15 - Typical CPU Timing Diagram for a CPU Read Cycle
Valid tim e
Symbol
Table 14 - AC Characteristics - CPU Read Cycle
T
T
T
T
T
T
T
RS
RS
RA
RH
RR
DV
DI
AD D R 0
T
Activ e Tim e
DV
(SCLK=100 Mhz)
T
Min.
RA
10
20
30
Zarlink Semiconductor Inc.
2
D ATA0
ZL50405
T
T
122
Max.
DI
RH
12
10
R ecov ery Tim e
Inv alid tim e
T
(SCLK=50 Mhz)
RR
Min.
10
40
60
2
T
RS
Max.
12
10
AD D R 1
T
Activ e Tim e
DV
T
P_A and P_CS# to falling
edge of P_RD#
At least 2 SCLK cycles
P_A and P_CS# to rising
edge of P_RD#
At least 3 SCLK cycles
P_DATA to falling edge of
P_RD#
P_DATA to rising edge of
P_RD#
RA
D ATA1
Refer to Figure 15
T
T
DI
RH
Data Sheet