zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 72

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.1.4
I²C Address: 01E+n; CPU Address:0081+2n (n = port number)
Accessed by CPU and I²C (R/W)
Port 0 – 3: (RMAC Ports)
Bit [0]:
Bit [1]:
Bit [2]:
Bits [4:3]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [7]
ECR4Pn: Port n Control Register
Link Heart Beat Transmit (RMAC ports only)
0: Disable (Default)
1: Enable
Enable TXCLK output. Active high
0: Disable (Default)
1: Mn_TXCLK pin becomes output in GPSI or MII mode
Enable RXCLK output. Active high
0: Disable (Default)
1: Mn_RXCLK pin becomes output in GPSI or MII mode
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Interface mode:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Link Heart Beat Receive
0: Disable (Default). Also clears all MAC LHB status.
1: Enable
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
00 - GPSI mode
01 - MII mode
10 - Reserved
11 - RMII mode (Default)
Zarlink Semiconductor Inc.
ZL50405
72
Data Sheet