zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 100

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7.4
CPU Address:h603
Accessed by CPU (R/W)
Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
12.3.7.5
CPU Address:h604
Accessed by CPU (R/W)
Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
12.3.7.6
CPU Address:h605
Accessed by CPU (R/W)
Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
12.3.7.7
CPU Address:h606
Accessed by CPU (R/W)
Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command. Writing this register will initiate a serial management cycle to the MII management
interface.
Bits [4:0]
Bit [5]
Bit [6]
Bit [7]
Bits [7:0]:
Bits [7:0]:
Bits [4:0]
Bits [6:5]
Bits [7]
MIIC0 – MII Command Register 0
MIIC1 – MII Command Register 1
MIIC2 – MII Command Register 2
MIIC3 – MII Command Register 3
PHY_AD – 5 Bit PHY Address
Reserved
VALID – Data Valid from PHY (Read Only)
RDY – Data is returned from PHY (Read Only)
REG_AD – Register PHY Address
OP – Operation code “10” for read command and “01” for write command
Reserved
MII Command Data [7:0]
MII Command Data [15:8]
Zarlink Semiconductor Inc.
ZL50405
100
Data Sheet