zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 130

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

14.0
14.1
•
14.2
•
•
•
•
•
•
•
•
•
14.3
•
•
•
•
•
•
•
14.4
•
•
•
•
14.5
•
•
•
Initial Release
Clarified IP Multicast support is up to 4K groups, as it wasn’t mentioned in the data sheets
Updated Ball Signal Description Table:
•
•
•
Updated Section 1.4 on page 17 to indicate operation of the internal pull-up/down resistors in different
modes
Clarified Section 10.1.3 on page 50 on usage of REF_CLK
Clarified PVMODE register bit description for bits [2] & [5]
Updated ECR4Pn register description as port 9 (uplink) operates differently than the RMAC ports for MII
bi-directional clocking (bits [1:0])
I
Added Maximum Junction Temperature to Section 13.1 on page 118
Updated I/O voltage levels to use TTL spec values rather than % of Vcc
Added the following to the Feature List:
•
•
•
Added section on PHY addresses
•
Fixed error in DS on sending Ethernet Frames via 8/16-bit or serial interface.
•
Added more cross-references to available AppNotes
Added section on Stacked VLAN (Q-in-Q) and IP Multicast Switching since they weren’t really discussed in
the DS
Added more clock descriptions to “Clocks” on page 49
INT_MASK and INTP_MASK registers should state that the default register value is 0x00
Added Errata List to document
Added section on SCL clock generation
Interrupt Register was incorrectly identified as read only, should be read/write
•
Updated CPU timing diagrams to clarify timing
Added section “Default Switch Configuration and Initialization Sequence” on page 21
Updated CPU timing diagrams to clarify P_A timing
Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable
2
C address mapping was corrected for QOSCn registers
clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either
inputs OR outputs
clarified that M9_MTXCLK is an input only
ball assignments for the Fast Ethernet Access Ports [3:0] MII signals were incorrect
4K jumbo frames
IEEE 802.3ad support
Reverse MII/GPSI
Clarified that they are hard-coded
The Status Bytes is sent before the frame, for both Tx and Rx
Clarified that only bit [7] is not self-clearing
July 2003
November 2003
February 2004
August 2004
November 2004
Document History
Zarlink Semiconductor Inc.
ZL50405
130
Data Sheet