zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 30

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

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In summary, access to the many internal registers is carried out simply by directly accessing only two registers –
one register to indicate the index of the desired parameter, and one register to read or write a value. Of course,
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
3.1.2
In serial mode with MII, the MII interface is used for CPU to transmit and receive Ethernet frames. In 8/16-bit or
serial only mode, the Ethernet frame is transmitted and received through the CPU interface. There is no ability to
send/receive Ethernet frames in unmanaged mode.
To transmit a frame from the CPU in 8/16-bit or serial only mode:
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To receive a frame into the CPU in 8/16-bit or serial only mode:
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To transmit a frame from the CPU with MII interface:
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To receive a frame into the CPU with MII interface:
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R/W
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INC
Similarly, to read the value in the register addressed by the index register(s), the “data” register can now
simply be read.
The ZL50405 supports an incremental read/write. If CPU requires to read or write to the configuration
registers incrementally, CPU only has to write to index register once with the MSB of configuration register
address set and then CPU can continuously reading or writing to “data” register (010b).
The CPU writes to the “data frame” register (address 011) with the frame size, destination port number, and
frame status. After writing all the transmitting status bytes, it then writes the data it wants to transmit
(minimum 64 bytes).
The ZL50405 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size, and
VLAN tag.
The actual data follows the frame information. The CPU uses the frame size information to read the frame
out.
ZL50405 acts as a PHY to provide receive clock (RXCLK) to CPU so the CPU will depend on this receive
clock to send packets to ZL50405
ZL50405 has the ability to halt the receive clock if the receive FIFO of ZL50405 is overflow. Transmitting from
CPU to ZL50405 will resume once the receive FIFO of ZL50405 is no longer overflow
Follow the standard Ethernet transmission format. CPU assert receive data valid (RXDV) before transmitting
data to ZL50405 and de-assert RXDV after transmitting the last data
ZL50405 acts as a PHY to provide transmit clock (TXCLK) to CPU so the CPU will depend on the transmit
clock to receive packets from ZL50405
ZL50405 has the ability to halt the transmit clock if the transmit FIFO of ZL50405 is under-run. CPU will
resume receiving packets from ZL50405 once the transmit FIFO of ZL50405 is no longer under-run
Follow the standard Ethernet transmission format. CPU will see transmit enable (TXEN) be asserted by
ZL50405 and CPU can start receiving data. CPU will stop receiving data once TXEN is de-asserted by
ZL50405.
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The ZL50405 supports special register-write in serial and 16-bit mode. This allows CPU to write to two
consecutive configuration registers in a single write operation. By writing to bit[14] of configuration
register address, CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address
specified in index register and upper 8 bit of data is for the address + 1. In 8-bit mode, this special feature
will be ignored.
Rx/Tx of Standard Ethernet Frames
SP
14
W
13
Reserved
12
11
Zarlink Semiconductor Inc.
ZL50405
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12 Bit Register Address
Data Sheet
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