zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 101

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7.8
CPU Address:h607
Accessed by CPU (RO)
12.3.7.9
CPU Address:h608
Accessed by CPU (RO)
12.3.7.10
CPU Address:h609
Accessed by CPU (R/W)
12.3.7.11
CPU Address:h60A
Accessed by CPU (R/W)
12.3.7.12
I²C Address 0FF, CPU Address:h60B
Accessed by CPU and I²C (R/W)
Bits [5:0]:
Bits [7:6]:
Bits [7:0]:
Bits [7:0]:
Bit [0]:
Bit [1]:
Bits [7:2]:
Bits [7:0]:
MIID0 – MII Data Register 0
MIID1 – MII Data Register 1
DEVICE Mode
USD – One Micro Second Divider
CHECKSUM - EEPROM Checksum
In a MII or GPSI system, a 50 MHz M_CLK may not be available. The system designer can
decide to use another frequency on the M_CLK signal. To compensate for this, this register
For example. If 20 MHz is used on M_CLK, to compensate for the difference, this register is
Divider to get one micro second from M_CLK (only used when not in standard RMII mode)
is required to be programmed.
programmed with 20 to provide 1usec for internal reference.
Reserved
MII Data [15:8]
MII Data [7:0]
Reserved
CPU Interrupt Polarity
0: Negative Polarity
1: Positive Polarity (Default)
Reserved
Checksum content (Default 0)
Zarlink Semiconductor Inc.
ZL50405
101
Data Sheet