zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 24

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

2.2.1.1
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX
data and respectively. The link and duplex of the port can be controlled by programming the ECR1Pn register. Only
port-based VLAN is supported with GPSI interface.
2.2.2
The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external CPU device. It support either a Reverse MII interface, providing the necessary
interface TX and RX clocks to the CPU, or a register access mechanism via the 8/16-bit or serial interface.
Using the MII interface, the CMAC of the ZL50405 device meets the IEEE 802.3 specification. It is able to operate
in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically
retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 8.
2.2.3
The MII Media Access Control (MMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). The MMAC implements an MII interface.
The MMAC of the ZL50405 device meets the IEEE 802.3 specification. It is able to operate in 10 M/100 M either
Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit
upon collision for up to 16 total transmissions.
This port is denoted as port 9. The PHY address for the PHY device connected to the MMAC port has to be 10h.
2.2.4
The table below provides an overview of the PHY addresses required for each port in order for the MDIO
auto-negotiation to work between the ZL50405 MAC and the PHY device. If a different PHY address is used, then
the port must be manually brought up and the PHY will need to be polled for link status via the MIIC/D registers.
2.3
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
This module is only active in managed mode. In unmanaged mode, no control frame is accepted by the device.
Management Module
CPU MAC Module (CMAC)
MII MAC Module (MMAC)
PHY Addresses
GPSI (7WS) Interface
RMAC Port 0
RMAC Port 1
...
RMAC Port 3
CMAC Port 8
MMAC Port 9
MAC Port
Table 5 - PHY Addresses
Zarlink Semiconductor Inc.
ZL50405
24
PHY Address
0x08
0x09
...
0x0B
NA
0x10
Data Sheet