zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 74

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.1.5
CPU Address:h036
Accessed by CPU (R/W)
12.3.1.6
CPU Address:h037
Accessed by CPU (R/W)
Bits [2:0]:
Bits [7:3]:
Bits [6:0]:
Bit [7]:
Bit [2]:
Bits [4:3]:
Bit [5]:
Bit [6]:
Bit [7]:
BUF_LIMIT – Frame Buffer Limit
FCC – Flow Control Grant Period
Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40)
Reserved
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Interface mode:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Reserved
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
Flow Control Grant Period (Default 0x3)
Reserved
11 - MII mode (Default)
Zarlink Semiconductor Inc.
ZL50405
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Data Sheet