zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 70

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zl50405

Manufacturer Part Number
zl50405
Description
Managed5-port 10/100 M Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
12.3.1.2
I²C Address: 00A+n; CPU Address:0001+2n (n = port number)
Accessed by CPU and I²C (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]
Bit [5]
Bits [7:6]
ECR2Pn: Port n Control Register
SS - Spanning tree state (IEEE 802.1D spanning tree protocol)
00 - Blocking:
01 - Listening:
10 - Learning:
11 - Forwarding:
Filter untagged frame
0: Disable (Default)
1: All untagged frames from this port are discarded or follow security option when
security is enable
Filter Tag frame
0: Disable (Default)
1: All tagged frames from this port are discarded or follow security option when
security is enable
Learning Disable
0: Learning is enabled on this port (Default)
1: Learning is disabled on this port
Rate control timer select (RMAC ports only)
0: 10 microsecond refreshing time (Default)
1: 1 millisecond refreshing time
0
Do not change VLAN tag. This overrides PVMAPnn_3 bit [2]. If this bit is set, no
tag will be replaced nor removed.
0: Disable (Default)
1: Enable
Frame is dropped
Frame is dropped
Frame is dropped. Source MAC address is learned.
Frame is forwarded. Source MAC address is learned. (Default)
Zarlink Semiconductor Inc.
ZL50405
70
Data Sheet

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