zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 109

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zl50405

Manufacturer Part Number
zl50405
Description
Managed5-port 10/100 M Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
12.3.10.7
CPU Address EA0+n
Accessed by CPU (RO)
12.3.10.8
CPU Address EA8 – EA9
Accessed by CPU (RO)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [8]:
Bit [9]:
Bit [10]:
Bit [5]:
Bit [6]
Bit [7]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
PRTQOSST0-PRTQOSST3
PRTQOSST8A, PRTQOSST8B (CPU port)
Reserved
LHB frame detected
LHB receiving timeout
Source port reservation low
No source port buffer left
Unicast congestion detected on best effort queue
Reserved
High priority queue reach L1 WRED level
High priority queue reach L2 WRED level
Low priority MC queue full
High priority MC queue full
Source port reservation low
No source port buffer left
Unicast congestion detected on best effort queue
Reserved
priority queue 1 reach L1 WRED level
priority queue 1 reach L2 WRED level
priority queue 2 reach L1 WRED level
priority queue 2 reach L2 WRED level
priority queue 3 reach L1 WRED level
priority queue 3 reach L2 WRED level
priority 0 MC queue full
15
PQSTB
Zarlink Semiconductor Inc.
ZL50405
109
PQSTA
0
Data Sheet

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