zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 92

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.6.19
I²C Address h05D, CPU Address:h543
Accessed by CPU and I²C (R/W)
Map TOS into frame discard when low priority buffer usage is above threshold
12.3.6.20
I²C Address h0B3+n, CPU Address:h550+n
Accessed by CPU and I²C (R/W)
(Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight
separate protocols.
12.3.6.21
I²C Address h0BB, CPU Address 558
Accessed by CPU and I²C (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bits [7:0]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
TOSDML – TOS Discard Map
USER_PROTOCOL_n – User Define Protocol 0~7
USER_PROTOCOL_FORCE_DISCARD – User Define Protocol 0~7 Force Discard
Frame drop priority when TOS field is 0 (Default 0)
Frame drop priority when TOS field is 1 (Default 0)
Frame drop priority when TOS field is 2 (Default 0)
Frame drop priority when TOS field is 3 (Default 0)
Frame drop priority when TOS field is 4 (Default 0)
Frame drop priority when TOS field is 5 (Default 0)
Frame drop priority when TOS field is 6 (Default 0)
Frame drop priority when TOS field is 7 (Default 0)
User Define Protocol
Enable Protocol 0 Force Discard
1 – Enable
0 – Disable
Enable Protocol 1 Force Discard
Enable Protocol 2 Force Discard
Enable Protocol 3 Force Discard
Enable Protocol 4 Force Discard
Enable Protocol 5 Force Discard
Enable Protocol 6 Force Discard
Zarlink Semiconductor Inc.
ZL50405
92
Data Sheet