zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 102

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

This register is used in unmanaged mode only. Before requesting that the ZL50405 updates the EEPROM device,
the correct checksum needs to be calculated and written into this checksum register.
The checksum formula is:
When the ZL50405 boots from the EEPROM the checksum is calculated and the value must be zero. If the
checksum is not zeroed the ZL50405 does not start and pin CHECKSUM_OK is set to zero.
12.3.7.13
CPU Address:h610
Accessed by CPU (R/W)
In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in half
this period. The receiver will trigger LHB timeout interrupt if not receiving any good packet in this period.
12.3.7.14
CPU Address:h611, h612
Accessed by CPU (R/W)
The LHB frame uses MAC control frame format (same as flow control frame.) The register here defines the
operation code (we recommend h00-12).
12.3.7.15
CPU Address:h613, h614
Accessed by CPU (R/W)
The registers define the operation code if MAC control frame is forced out by processor.
12.3.7.16
I²C Address 0BF, CPU Address:h620
Accessed by CPU and I²C (R/W)
12.3.7.17
I²C Address 0C0, CPU Address:h621
Accessed by CPU and I²C (R/W)
Bits [7:0]
Bits [7:0]
LHBTimer – Link Heart Beat Timeout Timer
LHBReg0, LHBReg1 - Link Heart Beat OpCode
fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
FCB Base Address Register 0
FCB Base Address Register 1
FF
$
i = 0
I²C register = 0
FCB Base address bit 7:0 (Default 0)
FCB Base address bit 15:8 (Default 0x60)
Zarlink Semiconductor Inc.
ZL50405
102
Data Sheet