zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 114

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

CPU address EC6
Accessed by CPU (R/W)
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
Note : There are two ways to reprogram the free granules.
1. CPU links all the granules: CPU writes memory directly, at last write head pointer (address EC1, EC2), tail
2. CPU tells Buffer Manager to link: CPU clear head pointer (address EC1, EC2), clear tail pointer (address EC3,
12.3.10.20
CPU address EC7
Accessed by CPU (R/W)
The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA,
EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit
0 is changing from 0 to 1.
12.3.10.21
CPU address EC8
Accessed by CPU (RO)
CPU address EC9
Accessed by CPU (RO)
CPU address ECA
Accessed by CPU (RO)
pointer (address EC3, EC4) and granule number (address EC5, EC6).
EC4), then write granule number that tells Buffer Manager to link (address EC5, EC6).
Bits [7:0]
Bits [6:0]
Bit [7]
Bits [7:0]
Bits [6:0]
Bit [7]
Bit [0]
Bits [7:1]
BM_RLSFF_CTRL
BM_RSLFF_INFO[5:0]
Fcb_number[14:8]. The total number of granules that CPU assigns.
Set 1 to write
Read BM release FIFO.
Reserved
Rls_head_ptr[7:0].
Rls_tail_ptr[0]
Rls_head_ptr[14:8].
Rls_tail_ptr[8:1]
Zarlink Semiconductor Inc.
ZL50405
114
Data Sheet