zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 105

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.9.2
I²C Address h05E+n, CPU Address:h820+n (n = port number)
Accessed by CPU and I²C (R/W)
This broadcast and multicast rate defines for Port n, the number of packets allowed to be forwarded within a
specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field
to 0. Time base is based on register FCR0 [6:4]
12.3.9.3
I²C Address h06A+n, CPU Address 840+n (n = port number)
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.4
I²C Address h073, CPU Address 848
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.5
I²C Address h072, CPU Address 849
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x24)
12.3.9.6
I²C Address h0C2+n, CPU Address 860+n (n = port number)
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
12.3.9.7
I²C Address h0CB, CPU Address 868
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
Bits [3:0]:
Bits [7:4]:
BMRCn - Port 0~3,8,9 Broadcast/Multicast Rate Control
PR100_n – Port 0~3 Reservation
PR100_CPU – Port CPU Reservation
PRM – Port MMAC Reservation
PTH100_n – Port 0~3 Threshold
PTH100_CPU – Port CPU Threshold
Multicast Rate Control. Number of multicast packets allowed within the time defined in
bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0).
Broadcast Rate Control. Number of broadcast packets allowed within the time defined
in bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0)
Zarlink Semiconductor Inc.
ZL50405
105
Data Sheet