SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 94

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
Table 82:
T
9397 750 13138
Product data sheet
Symbol
Interrupt timing (see
t
Clock timing (see
t
f
t
f
t
f
f
t
f
f
Transmitter timing (see
t
t
Receiver timing (see
t
t
68000 (Motorola) bus timing (see
t
t
d(int)
CLK
X1/SCLK
CTC
CTC
RX
RX(16)
RX(1)
TX
TX(16)
TX(1)
d(o)(TXD)
TCS
su(RXD-RXCH)(D)
h(RXCH-RXD)(D)
su(RWL-CEN)(mot)
su(D)(mot)
amb
= 40 C to +85 C; voltage tolerance
Dynamic characteristics
Parameter
interrupt delay time
X1/SCLK HIGH or LOW time
clock frequency on pin X1/SCLK 7.0 MHz to 16.2 MHz with
Counter/Timer clock HIGH or
LOW time
Counter/Timer clock frequency
RxC HIGH or LOW time (16X)
RxC frequency (16X)
RxC frequency (1X)
TxC HIGH or LOW time
TxC frequency (16X)
TxC frequency (1X)
TxC LOW to TXD output delay
time
TxC output pin LOW to
TXD data output delay time
RXD to RxC HIGH data setup
time
RxC HIGH to RXD data hold
time
CEN LOW to RWN setup time
data bus to X1/SCLK HIGH
setup time
Figure
Figure
Figure 16
Figure 15
14,
13)
Figure
and
Figure
and
Figure
…continued
15, and
Figure
9,
10 %; unless otherwise specified.
18)
Figure
Figure
17)
Rev. 01 — 31 October 2005
Conditions
IRQN (or I/O[7:3]B when
used as interrupts) negated
from
crystal
IP2; C/T external clock input
IP2
TxC input pin
10, and
read RxFIFO
(RxRDY/FFULL interrupt)
write TxFIFO
(TxRDY interrupt)
reset command (delta
break change interrupt)
stop C/T command
(Counter/Timer interrupt)
read IPCR (delta input
port change interrupt)
write IMR (clear of change
interrupt mask bit(s))
16)
Figure
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
11)
[1]
[5] [6]
[5] [6]
[5]
[7]
V
Min
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
10
10
10
10
20
20
10
DD
1
0
0
0
0
0
5
-
-
-
-
-
-
-
-
= 3.3 V
Max
1.5
1.5
40
40
40
40
40
40
34
24
24
40
40
8
-
-
-
-
-
-
-
SC28L201
Min
10
20
20
10
V
8
1
0
8
0
0
8
0
5
-
-
-
-
-
-
-
-
-
DD
= 5 V
Max
30
30
30
30
30
30
50
20
50
50
30
30
3
3
-
-
-
-
-
-
-
94 of 110
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
ns
ns
ns
ns
ns
ns