SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 84

IC UART W/FIFO 48-TSSOP

SC28L201A1DGG,118

Manufacturer Part Number
SC28L201A1DGG,118
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet

Specifications of SC28L201A1DGG,118

Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277824118
SC28L201A1DGG-T
SC28L201A1DGG-T
Philips Semiconductors
9397 750 13138
Product data sheet
8.6.12 Output Port Register A and B (OPR)
The I/O pins drive the logical inverse of the data in this register.
Table 75:
n = A for A, n = B for B
The I/O pins, when their control code in the IOPCR is set to code 01, drive the inverse
level of the data in the OPR register. This register is not readable and its value is
controlled by the SOPR and ROPR described in
Bit
7
6
5
4
3
2
1
0
Symbol
OPR A, OPR B - Output Port Register A and B bit description
Description
I/O7 n
I/O6 n
I/O5 n
I/O4 n
I/O3 n
I/O2 n
I/O1 n
I/O0 n
Rev. 01 — 31 October 2005
0 = pin HIGH
1 = pin LOW
0 = pin HIGH
1 = pin LOW
0 = pin HIGH
1 = pin LOW
0 = pin HIGH
1 = pin LOW
0 = pin HIGH
1 = pin LOW
0 = pin HIGH
1 = pin LOW
0 = pin HIGH
1 = pin LOW
0 = pin HIGH
1 = pin LOW
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Section 8.6.10
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
and
SC28L201
Section
8.6.11.
84 of 110

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