SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 49

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
9397 750 13138
Product data sheet
8.2.5 Receiver Clock Select Register (RxCSR) and Transmitter Clock Select
Table 19:
[1]
Register (TxCSR)
Table 20:
Both registers consist of single 6-bit field that selects the clock source for the receiver and
transmitter respectively. During a read the unused bits in this register read ‘000’. The
‘BRG’ baud rates (fixed BRG rates) shown in
frequency of 14.7456 MHz. The baud rates shown in
crystal clock varies. For example, if the SCLK rate is changed to 7.3728 MHz all the rates
below will reduce by
Bit
1:0
Bit
7:6
5:0
If this bit is not ‘0’, the characters will be stripped regardless of bits [3:2] or [1:0].
Symbol
Symbol
-
-
MR3 - Mode Register 3 (address 0x23) bit description
RxCSR - Receiver Clock Select Register (address 0x30) and
TxCSR - Transmitter Clock Select Register (address 0x31) bit description
Description
Address Recognition control.
This field controls the operation of the Address recognition logic. If the device
is not operating in the special or Wake-up mode, this hardware may be used
as a general-purpose character detector by choosing any combination except
00. Interrupt generation is controlled by the channel IMR. The interrupt may be
cleared by a read of the XISR, the Xon/Xoff Interrupt Status Register. See
further description in
Description
reserved
Transmitter/Receiver Clock Select code; see
00 = default
01 = Auto wake
10 = Auto doze
11 = Auto wake and Auto doze
1
Rev. 01 — 31 October 2005
2
.
Section 7.4.7.6 “Wake-up
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Table 21
Table 21
are based on the SCLK crystal
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
mode”.
will vary as the SCLK
…continued
21.
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