SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 11

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
9397 750 13138
Product data sheet
6.1.4 UART
6.1.5 Transmitter and receiver
6.1.6 Transmitter real time error check
6.1.7 FIFO structures
6.1.8 Intelligent interrupt arbitration
The UART is a fully independent, full duplex and provides all normal asynchronous
functions: 5 to 8 data bits, parity odd or even, programmable stop bit length, false start bit
detection. Also provided are 256-byte FIFOs, Xon/Xoff software flow control, RTS/CTS
hardware flow control. The 9-bit mode address recognition with automatic RS485
turnaround. The BRG, Counter/Timer, or external clocks provide the baud rates. The
receivers and transmitters may operate in either the ‘1 ’ or ‘16 ’ modes.
The control section recognizes two address schemes. One is the subset of the other: a
four (4) bit and a seven (7) bit address spaces. The purpose of this is to provide a large
degree of software compatibility with previous Philips/Signetics UARTs.
The transmitter and receiver are independent devices capable of full duplex operation.
Baud rates, interrupt and status conditions are under separate control. Transmitter has
automatic simplex ‘turnaround’. Receiver has RTS and Xon/Xoff flow control and a
three-character recognition system.
This is a circuit used to verify that the correct data arrived at the destination. It is done real
time with one or two bit times of programmable delay. The purpose of this circuit is to
improve the response time of detecting problem data channels and to relieve the
processor burden and delay of checking data returned for validation.
The function is that the receiver returns the data received back to the transmitting station
where it is compared to a delayed version of the data sent. If an error occurs, and interrupt
may be generated for the particular bit that is in error. This is essentially a loopback
condition where circuits internal to the UART delay and compare the data returned.
It is suggested that a very high priority be set in the interrupt arbitration bidding control
register when the real time error detection is in use.
The FIFO structure is 256 bytes for each of the two FIFOs in the UART. They are
organized as 11-bit words for the receiver and 8-byte words for the transmitter. The
interrupt level may be set at any value from 0 to 255. The interrupt level is independently
set for each FIFO.
FIFO interrupt and DMA fill/empty levels are controlled by the RXFIL and TXFIL registers
which may set any level of the from 0 to 255. The signals associated with the FIFO fill
levels are available to the I/O pins (for interrupt or DMA) and to the arbitrating interrupt
system for fine tuning of the arbitration authority.
The interrupt system uses a highly programmable arbitrating technique to establish when
an interrupt should be presented to the processor. The advantageous feature of this
system is the presentation of the context of the interrupt. It is presented in both a current
interrupt register and in the interrupt vector. The context of the interrupt shows the
interrupting channel, identifies which of the 11 possible sources in requesting interrupt
service and in the case of a receiver or transmitter gives the current fill level of the FIFO.
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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