SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 57

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
9397 750 13138
Product data sheet
Table 25:
Bit
1
0
Symbol
RxINT
TxINT
ISR - Interrupt Status Register (address 0x25) bit description
Description
Receiver entered the arbitration process. (Also Rx DMA hand-shake at I/O
pins.)
The general function of this bit is to indicate that the RxFIFO has data available
and that it has entered the arbitration process. The particular meaning of this bit
is programmed by RxFIL register. If programmed as receiver ready
(MR2[3:2] = 00), it indicates that at least one character has been received and
is waiting in the RxFIFO to be read by the host CPU. It is set when the
character is transferred from the receive shift register to the RxFIFO and reset
when the CPU reads the last character from the RxFIFO.
If RxFIL is programmed as FIFO full, ISR[1] is set when a character is
transferred from the receive holding register to the RxFIFO and the transfer
causes the RxFIFO to become full, that is, all 256 FIFO positions are occupied.
It is reset whenever RxFIFO is not full. If there is a character waiting in the
receive shift register because the FIFO is full, the bit is set again when the
waiting character is transferred into the FIFO.
The other two conditions of these bits,
manner. The ISR[1] bit is set when the RxFIFO fill level meets or exceeds the
value; it is reset when the fill level is less. See the description of the MR2
register.
Remark: This bit must be at a one (1) for the receiver to enter the arbitration
process. It is the fact that this bit is zero (0) when the RxFIFO is empty that
stops an empty FIFO from entering the interrupt arbitration. Also note that the
meaning if this bit is not quite the same as the similar bit in the Status Register
(SR).
pins.)
The general function of this bit is to indicate that the TxFIFO has an at least one
empty space for data. The particular meaning of the bit is controlled by MR0
[5:4] indicates the TxFIFO may be loaded with one or more characters. If
MR0[5:4] = 00 (the default condition) this bit will not set until the TxFIFO is
empty: 256 bytes available. If the fill level of the TxFIFO is below the trigger
level programmed by the TxINT field of the Mode Register 0, this bit will be set.
A one in this position indicates that at least one character can be sent to the
TxFIFO. It is turned off as the TxFIFO is filled above the level programmed by
MR0[5:4]. This bit turns on as the FIFO empties. (Note that the RxFIFO bit
turns on as the FIFO fills.) This often a point of confusion in programming
interrupt functions for the receiver and transmitter FIFOs.
Remark: This bit must be at a one (1) for the transmitter to enter the arbitration
process. It is the fact that this bit is zero (0) when the TxFIFO is full that stops a
full TxFIFO from entering the interrupt arbitration. Also note that the meaning if
this bit is not quite the same as the similar bit in the status register (SR).
Transmitter entered the arbitration process. (Also Tx DMA hand-shake at I/O
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
3
4
and
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
1
2
full operate in a similar
SC28L201
…continued
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