SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 33

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
9397 750 13138
Product data sheet
7.4.10.1 Mode control
7.4.9.1 Character stripping
7.4.10 Flow control (Xon/Xoff)
Remark: Reading the XISR Clears the status bits associated with the recognition.
The characters of the recognition system are fully programmable. The Xon/Xoff
characters will be set to the standard characters if the hardware or software reset is used.
The character recognition circuits are basically designed to provide general-purpose
character recognition. Additional control logic has been added to allow for Xon/Xoff flow
control and for recognition of the address character in the multi-drop or Wake-up mode.
This logic also allows for the generation of interrupts in either the general-purpose
recognition mode or the specific conditions mentioned above.
The generality of the above provides a modicum of compatibility to BOP (Bit Oriented
Protocol) where the generation and detection of ‘flags’ is required. Parts of usually
synchronous BOP protocols (HDLC in particular) are beginning to show up in
asynchronous formats.
The MR0[7:6] register provides for stripping (meaning not set to the RxFIFO) the
characters used for character recognition. Recall that the character recognition may be
conditioned to control several aspects of the communication. However this system is first a
character recognition system. The status of the various states of this system is reported in
the XISR and ISR registers. The character stripping of this system allows for the removal
of the specified control characters from the data stream: two for the Xon /Xoff and one for
the wake-up. Via control in the MR0[7:6] register these characters may be discarded
(stripped) from the data stream when the recognition system ‘sees’ them or they may be
sent on the RxFIFO. Whether they are stripped or not the recognition system will process
them according to the action requested; flow control, wake-up, interrupt generation, and
so on. Care should be exercised in programming the stripping option if noisy
environments are encountered. If a normal character were corrupted to an Xoff character
the transmitter would be stopped. If that character were now stripped from the FIFO stack,
then that stripping action would make it difficult to determine the cause of transmitter
stopping.
When character stripping is invoked and a recognition character is received that has an
error bit set that character is sent to the RxFIFO even though character stripping is
active.
This section describes in-band flow control or Xon/Xoff signaling. For the RTS/CTS
hardware (out-of-band) control see MR1[7] and MR2[4] descriptions.
The flow control is accomplished via the character recognition system giving recognition
information to the flow control processor. Xon and Xoff are special characters used by a
receiver to start and stop the remote transmitter that is sending it data. Several modes of
manual and automatic flow control are available by programming mode control.
Xon/Xoff mode control is accomplished via the MR3[3:2].
00 — Xon/Xoff processing disabled. The host will control Rx, Tx.
01 — Auto Tx control. Tx is stopped/started when Xoff/Xon is received.
10 — Auto Rx control. Receiver commands Tx to send Xoff at trigger level.
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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