MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 874

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-117
14.5.3.11.4 Timer PTP Packet Event Register (TMR_PEVENT)
The eTSEC precision timer logic can generate interrupts upon the capture of a timestamp due to either
transmission or reception of a frame. If an event occurs and its corresponding enable bit is set in the event
mask register (PEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event
register is cleared by writing a 1 to that bit position. Figure 14-112 describes the definition for the
TMR_PEVENT register.
14-126
Offset eTSEC1:0x2_4E08
Reset
Reset
16–23
26–31
8–13
Bits
0–5
14
15
24
25
6
7
W
W
R
R
16
0
ALM2EN
ALM1EN
ETS2EN
ETS1EN
PP1EN
PP2EN
Name
describes the fields of the TMR_TEMASK register fields for the timer.
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Reserved
External trigger 2 timestamp sample event enable
External trigger 1 timestamp sample event enable
Reserved
Timer ALM1 event enable
Timer ALM2 event enable
Reserved
Periodic pulse event 1 enable
Periodic pulse event 2 enable
Reserved
Table 14-117. TMR_TEMASK Register Field Descriptions
—
Table 14-116. TMR_TEMASK Register Definition
5
ETS2EN ETS1EN
6
23
7
All zeros
All zeros
PP1EN PP2EN
24
8
Description
25
—
26
Freescale Semiconductor
13
—
Access: Read/Write
ALM2EN ALM1EN
14
15
31