MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1127

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-23
Freescale Semiconductor
Bits
1–7
10
11
12
13
14
15
16
0
8
9
CDNSC Completion with data not successful. A completion with data packet was received with a non successful
CRSNC CRS non configuration. A completion was detected for a non configuration cycle and with CRS status.
Name
PCAC
CRST
ICCA
PNM
IACA
PCT
ME
—
—
describes the fields of the PCI Express error detect register.
Multiple errors. Detecting multiple errors of the same type. An error is considered as multiple error when its
detect bit is set and the same error is occurring again. Note that this bit does not track the ordering of when
the error occurs.
1 Multiple errors were detected.
0 Multiple errors were not detected.
Reserved
PCI Express completion time-out. A completion time-out condition was detected for a non-posted,
outbound PCI Express transaction. An error response is sent back to the requestor. Note that a completion
timeout counter only starts when the non-posted request was able to send to the link partner.
1 A completion time-out on the PCI Express link was detected. Note that a completion timeout error is a
0 No completion time-out on the PCI Express link detected.
Reserved
PCI Express completer abort (CA) completion. A completion with CA status was received.
1 A completion with CA status was detected.
0 No completion with CA status detected.
PCI Express no map. Detect an inbound transaction that was not mapped to any inbound windows. In RC
mode, a completion without data (Cpl) packet with a UR completion status is sent back to the requester and
this bit is set. For EP mode, a Cpl packet with a UR completion status is sent back to the requester but
does not set this bit.
1 A no-map transaction was detected in RC mode.
0 No no-map transaction detected.
status (that is, UR, CA or CRS status).
1 Completion with data non successful packet was detected.
0 No completion with data non successful packet detected.
1 CRS non configuration packet was detected.
0 No CRS non configuration packet detected.
Invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA configuration access. Access to an illegal
configuration space from PEX_CONFIG_ADDR/PEX_CONFIG_DATA was detected.
1 Invalid CONFIG_ADDR/PEX_CONFIG_DATA access detected
0 No invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access detected
Invalid ATMU configuration access. Access to an illegal configuration space from an ATMU window was
detected.
1 Invalid ATMU configuration access was detected
0 No invalid ATMU configuration access detected
CRS thresholded. An outbound configuration transaction was retried and thresholded due to a CRS
completion status. An error response is sent back to the requestor. See
Configuration Retry Timeout Register
1 A CRS threshold condition was detected for an outbound configuration transaction
0 No CRS threshold condition detected
fatal error. If a completion timeout error is detected, the system has become unstable. Hot reset is
recommended to restore stability of the system.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-23. PCI Express Error Detect Register Field Descriptions
(PEX_CONF_RTY_TOR),” for more information.
Description
Section 17.3.2.4, “PCI Express
PCI Express Interface Controller
17-31