MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 182

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.4.3.2
Table 4-10
between the e500 core clock and the e500 core complex bus (CCB) clock. Note that the values latched on
these signals during POR are accessible through the memory-mapped PORPLLSR, as described in
Section 23.4.1.1, “POR PLL Status Register (PORPLLSR),”
described in the PowerPC e500 Core Family Reference Manual and in
Integratation Details.”
4-12
LBCTL, LALE, LGPL2/LOE/LFRE
Functional Signals
describes the e500 core clock PLL inputs that program the core PLL and establish the ratio
Functional Signals
Default (111)
e500 Core PLL Ratio
Default (1111)
LA[28:31]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reset Configuration
Table 4-10. e500 Core Clock PLL Ratios
cfg_sys_pll[0:3]
Reset Configuration Name Value (Binary)
Table 4-9. CCB Clock PLL Ratio
Name
cfg_core_pll[0:2]
(Binary)
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
and also in the e500 core HID1 register, as
000
001
010
011
100
101
110
111
CCB Clock : SYSCLK Ratio
Section 5.3, “Summary of Core
Reserved (default)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
16 : 1
10 : 1
12 : 1
3 : 1
4 : 1
5 : 1
6 : 1
8 : 1
9 : 1
e500 Core: CCB ClockRatio
7 : 2 (3.5 : 1) (default)
Freescale Semiconductor
3 : 2 (1.5 : 1)
9 : 2 (4.5:1)
5 : 2 (2.5:1)
Reserved
4 : 1
2 : 1
3 : 1