MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1192

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
The fields of the PCI Express configuration ready register are described in
17.3.10.19 PME_To_Ack Timeout Register (RC-Mode Only)—0x590
The PCI Express PME_To_Ack timeout register, shown in
value for a PME_To_Ack message response in terms of PCI Express controller core clock cycles.
The fields of the PCI Express PME_To_Ack timeout register are described in
17.3.10.20 Secondary Status Interrupt Mask Register (RC-Mode Only)—0x5A0
The PCI Express secondary status interrupt mask register, shown in
sideband interrupt generation when error bits in the PCI Express secondary status register are set. See
Section 17.3.8.3.8, “PCI Express Secondary Status
interrupt generation due to secondary status errors is disabled.
17-96
Offset 0x590 (RC-mode only)
Reset 1
31–22
31–1
21–0
Bits
Bits
0
W
R
31
PME_TO_ACK
Figure 17-120. PCI Express PME_To_Ack Timeout Register (PEX_PME_TO_ACK_TOR)
CFG_READY
0
TIMEOUT
Name
Name
0
—
—
_
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
—
0
Reserved
After a PME_Turn_Off message is broadcast by the RC, the power management module waits
for the duration of the PME_To_Ack timeout interval to receive a PME_To_Ack message from
the downstream device. If the Ack message is not received within this interval, the power
manager indicates that it is safe to switch off power, since timeout has occurred.
The value is calculated as:
The recommended timeout duration is 1 msec to 10 msec to make sure that the downstream
devices get enough time to prepare for power-off condition.
Reserved
Configuration ready
1 The transaction layer accepts inbound configuration requests.
0 The transaction layer responds to all inbound configuration requests with retry (CRS)
Note that the reset state of this bit is determined during POR.
Table 17-117. PEX_PME_TO_ACK_TOR Field Descriptions
0
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
Table 17-116. PEX_CFG_READY Field Descriptions
0
0
22 21
0
0
0
0
0
0
Register—0x1E,” for more information. By default,
1
0
Description
Description
Figure
PME_TO_ACK_TIMEOUT
0
0
0
17-120, is used to program the timeout
Figure
0
1
0
17-121, can be used to disable
Table
0
Table
0
17-116.
0
Freescale Semiconductor
17-117.
1
Access: Read/Write
0
1
0
0
0
0