MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 332

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MPC8536-RDK

Manufacturer Part Number
MPC8536-RDK
Description
BOARD REF COMEXPRESS MPC8536
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets

Specifications of MPC8536-RDK

Contents
CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DDR Memory Controller
8.4.1.40
The memory error attributes capture register, shown in
type, size, source, and others.
Table 8-46
8.4.1.41
The memory error address capture register, shown in
a DDR ECC error is detected.
8-58
16–17
18–19
20–30
8–10
Bits
1–3
5–7
31
Offset 0xE4C
Reset
0
4
W
R
Offset 0xE50
Reset
BNUM Data beat number. Captures the doubleword number for the detected error. Relevant only for ECC errors.
Name
TTYP Transaction type for the error.
TSIZ
0
VLD
W
R
describes the CAPTURE_ATTRIBUTES fields.
1
Figure 8-41. Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)
0
Memory Error Attributes Capture (CAPTURE_ATTRIBUTES)
Memory Error Address Capture (CAPTURE_ADDRESS)
BNUM
Figure 8-42. Memory Error Address Capture Register (CAPTURE_ADDRESS)
Reserved
Reserved
Transaction size for the error. Captures the transaction size in double words.
000 4 double words
001 1 double word
010 2 double words
011 3 double words
Others Reserved
Reserved
Reserved
00 Reserved
01 Write
10 Read
11 Read-modify-write
Reserved
Valid. Set as soon as valid information is captured in the error capture registers.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
4
Table 8-46. CAPTURE_ATTRIBUTES Field Descriptions
5
TSIZ
7
8
10 11
TSRC
All zeros
All zeros
CADDR
Figure
15 16 17 18 19 20
Description
Figure
8-42, holds the 32 lsbs of a transaction when
8-41, sets attributes for errors including
TTYP
Access: Read/Write
Freescale Semiconductor
Access: Read/Write
30
31
VLD
31

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