MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 403

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.4.1
Each PMnMR0 register, shown in
Because each unreserved bit in the 96-bit vector (PMnMR0/1/2) specifies a different interrupt, only one
bit in the 96-bit vector can be unmasked at a time. Unmasking more than one bit per set is considered a
programming error and results in unpredictable behavior.
Table 9-27
Freescale Semiconductor
Offset PM0MR0: 0x1350; PM1MR0: 0x1370; PM2MR0: 0x1390; PM3MR0: 0x13B0
Reset 1
12–15 TIMER Timer interrupts 0–3 (Group A and Group B: Each bit represents an OR of the event for the
16–19 MSG Message interrupts 0–7
20–31
W
8–11
R
Bits
0–7
0
1
Name
MShI Shared message signaled interrupts 0–7
EXT External interrupts IRQ[]
describes the PMnMR0 fields.
IPI
1
Performance Monitor Mask Registers 0 (PM0MR0–PM3MR0)
MShI
1
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
Interprocessor interrupts 0–3
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
correspondingly numbered timer in Group A and that in Group B).
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
Bit 0 is used for MSG0 and MSG4
Bit 1 is used for MSG1 and MSG5
Bit 2 is used for MSG2 and MSG6
Bit 3 is used for MSG3 and MSG7
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 9-25. Performance Monitor Mask Registers 0 (PM n MR0)
1
1
7
1
1
8
Table 9-27. PM n MR0 Field Descriptions
Figure
1
IPI
1
11 12
1
9-25, is matched with a PMnMR1 and a PMnMR2 register.
1
TIMER
1
1
15 16
1
Description
1
MSG
1
1
19 20
1
1
1
Programmable Interrupt Controller (PIC)
1
1
1
1
EXT
1
Access: Read/Write
1
1
1
1
9-33
31
1