MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1540

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Global Utilities

The PMC allows several wake-up events source to exit low power mode, such as wake on LAN (magic

packet or user defined), USB, GPIO, and internal timer. The wake-up events are mapped to OpenPIC

interrupts to generate a wake-up interrupt to the PMC.

The MPC8536E has four low-power states: doze, nap, sleep and deep sleep. The mapping of core and

device power management states is shown in

of the e500 core.

For each operating state represented in the diagram, the cores state is listed first, with the corresponding

state of the MPC8536E shown beneath it in parenthesis. Note that there are many other variables that

control the state transitions between MPC8536E power management states. These additional variables are

described in more detail in

CKSTP_IN0/1 are not described here because they are not considered power management signals,

although asserting these do stop the cores and a stopped core is technically in a low-power mode.

CKSTP_IN0/1 are described in

Relationship Between Core and Device Power Management States

CKSTP_IN0/1 is Not Power Management

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 23-34. e500 Core Power Management State Diagram

Section 23.5.1.8, “Power-Down Sequence Coordination.”

core_stop & core_halt

Section 23.3.2, “Detailed Signal Descriptions.”

Figure 23-34

Core-Powered Off

Core-Stopped

(Deep Sleep)

showing state transitions from the perspective

core_halt & ¬ core_stop

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