MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 543

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.4.6
The DEU interrupt status register indicates which unmasked errors have occurred and have generated error
interrupts to the channel. Each bit in this register can only be set if the corresponding bit of the DEU
interrupt mask register is zero (see
If the DEU interrupt status register is non-zero, the DEU halts and the DEU error interrupt signal is
asserted to the controller (see
DEU is being operated through channel-controlled access, then an interrupt signal is generated to the
channel to which this EU is assigned. The EU error then appears in bit 55 of the channel status register
(see
If the interrupt status register is written from the host, 1s in the value written are recorded in the interrupt
status register if the corresponding bit is unmasked in the interrupt mask register. All other bits are cleared.
This register can also be cleared by setting the RI bit of the DEU reset control register.
The definition of each bit in the DEU interrupt status register is shown in
Table 10-51
Freescale Semiconductor
Offset DEU 0x3_2030
Reset
Table
W
R
0-49
Bits
50
51
52
53
0
10-15) and generates a channel error interrupt to the controller.
describes DEU interrupt status register fields.
DEU Interrupt Status Register
Name
KPE
ERE
CE
—
IE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-51. DEU Interrupt Status Register Field Descriptions
—
Reserved
Key Parity Error. Defined parity bits in the keys written to the key registers did not reflect
odd parity correctly. (Note that key register 2 and key register 3 are checked for parity only
if the appropriate DEU mode register bit indicates triple DES. Also, key register 3 is
checked only if key size reg = 24. Key register 2 is checked only if key size reg = 16 or 24.)
0 No error detected
1 Key parity error
Internal Error. An internal processing error was detected while performing encryption.
0 No error detected
1 Internal error
Note: This bit is asserted any time an enabled error condition occurs and can only be
Early Read Error. The DEU IV register was read while the DEU was performing encryption.
0 No error detected
1 Early read error
Context Error. A DEU key register or the key size register, data size register, mode register,
or IV register was modified while DEU was performing encryption.
0 No error detected
1 Context error
Section 10.5.4.2.2, “Interrupt Status Register
Figure 10-61. DEU Interrupt Status Register
cleared by setting the corresponding bit in the interrupt mask register or by resetting
the DEU.
Section 10.7.4.7, “DEU Interrupt Mask
49
KPE IE ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU OFO
50
51
All zeros
52
53
Description
54
55
56
Figure
Register”).
(ISR)”). In addition, if the
57
58
10-61.
59
Security Engine (SEC) 3.0
60
Access: Read only
61
62
10-113
63