MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 730

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
Figure 13-69
13.4.4.4.9
When the LAST bit is read in a RAM word, the current UPM pattern is terminated at the end of the current
cycle. On the next cycle (following LAST) all the UPM signals are negated unconditionally (driven to
logic 1), unless there is a back-to-back UPM request pending. In this case, the signal values for the cycle
following the one in which the LAST bit was set are taken from the first RAM word of the pending UPM
routine.
In case of UPM writes, program UTA and LAST in same RAM word. In case of UPM reads, program UTA
and LAST in consecutive or same RAM words.
13.4.4.4.10 Wait Mechanism (WAEN)
The WAEN bit in the RAM array word can be used to enable the UPM wait mechanism in selected UPM
RAM words. If the UPM reads a RAM word with WAEN set, the external LUPWAIT signal is sampled
and synchronized by the memory controller as if it were an asynchronous signal. The WAEN bit is ignored
if LAST = 1 in the same RAM word.
Synchronization of LUPWAIT starts at the rising edge of the bus clock and takes at least 1 bus cycle to
complete. If LUPWAIT is asserted and WAEN = 1 in the current UPM word, the UPM is frozen until
LUPWAIT is negated. The value of external signals driven by the UPM remains as indicated in the
previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during
WAIT cycles, the UPM does not handle data.
Figure 13-70
to hold the UPM in a particular state until LUPWAIT is negated. As the example shows, the LCSn and
LGPL1 states and the WAEN value are frozen until LUPWAIT is recognized as negated. WAEN is
13-88
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To internal
data bus
feature should be used only in systems without external synchronous bus devices that require
mid-cycle sampling.
If MxMR[GPL4] = 0 (G4T4/DLT3 functions as G4T4), or if MxMR[GPL4] = 1 but DLT3 = 0 in
the RAM word, data is latched on the rising edge of the bus clock, which occurs at the end of the
current bus clock cycle (normal operation).
shows how data sampling is controlled by the UPM.
shows how the WAEN bit in the word read by the UPM and the LUPWAIT signal are used
LGPL[0:5] Signal Negation (LAST)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
UPM read AND GPL4nDIS = 1 AND DLT3 = 1
Figure 13-69. UPM Read Access Data Sampling
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LCLK
Freescale Semiconductor
LAD[0:31]