MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1299

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 20-15
bits are set, it can be assumed that the response was not received correctly.
Freescale Semiconductor
CINS
Field
BWR
DINT
BRR
BGE
TC
CC
25
26
27
28
29
30
31
Card insertion. This bit is set if PRSSTAT[CINS] changes from 0 to 1. When the host driver writes 1 to this bit to clear
it, the status of PRSSTAT[CINS] should be confirmed. Because the card-detect state may be changed when the
host driver clears this bit, an interrupt event may not be generated.
When this bit is cleared, it is set again if a card has been inserted. To leave it cleared, clear IRQSTATEN[CINSEN].
0 Card state unstable or removed
1 Card inserted
Buffer read ready. This bit is set if PRSSTAT[BREN] changes from 0 to 1.
0 Not ready to read buffer
1 Ready to read buffer
Buffer write ready. This bit is set if PRSSTAT[BWEN] changes from 0 to 1.
0 Not ready to write buffer
1 Ready to write buffer
DMA interrupt. Occurs when the internal DMA finishes the data transfer successfully. If errors occur during data
transfer, this bit is not set. Instead, the DMAE bit is set.
0 No DMA interrupt
1 DMA interrupt is generated
Block gap event. If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction is stopped at a block
gap. If PROCTL[SABGREQ] is cleared, this bit is not set.
During a read transaction, this bit is set at the falling edge of the SDHC_DAT line active status (when the transaction
is stopped at SD bus timing). Read wait must be supported to use this function.
During a write transaction, this bit is set at the falling edge of PRSSTAT[WTA] (after reading the CRC status at SD
bus timing).
0 No block gap event
1 Transaction stopped at block gap
Transfer complete. This bit is set when a read or write transfer is completed.
For a read transaction, this bit is set at the falling edge of PRSSTAT[WTA]. There are two cases in which this interrupt
is generated:
For a write transaction, this bit is set at the falling edge of PRSSTAT[DLA]. There are two cases in which this interrupt
is generated:
Command complete. This bit is set when the end bit of the command response is received (except Auto CMD12).
Refer to PRSSTAT[CIHB].
0 No command complete
1 Command complete
• When a data transfer is completed, as specified by data length (after the last data has been read to the host
• When data has stopped at the block gap and completed the data transfer by setting PROCTL[SABGREQ] (after
• When the last data is written to the SD card, as specified by data length and the busy signal is released.
• When data transfers are stopped at the block gap by setting PROCTL[SABGREQ] and data transfers have
below shows that command timeout error has higher priority than command complete. If both
system).
valid data has been read to the host system).
completed (after valid data is written to the SD card and the busy signal is released).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-14. IRQSTAT Field Descriptions (continued)
Description
Enhanced Secure Digital Host Controller
20-25